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Bits 2 and 1—Reserved: These bits are always read as 0, and cannot be modified.
Bit 0—Reserved: In the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and
H8S/2314 F-ZTAT, this bit is always read as 0 and cannot be modified.
In the H8S/2319 F-ZTAT or H8S/2319C F-ZTAT, this bit is reserved and should only be written
with 0.
3.3
Operating Mode Descriptions
3.3.1
Mode 1 (H8S/2319C F-ZTAT Only)
This is a flash memory boot mode. See section 17, ROM, for details.
Except for the fact that flash memory programming and erasing can be performed, operation in
this mode is the same as in advanced single-chip mode.
3.3.2
Mode 2 (H8S/2319 F-ZTAT and H8S/2319C F-ZTAT Only)
This is a flash memory boot mode. See section 17, ROM, for details.
Except for the fact that flash memory programming and erasing can be performed, operation in
this mode is the same as in advanced expanded mode with on-chip ROM enabled.
3.3.3
Mode 3 (H8S/2319 F-ZTAT and H8S/2319C F-ZTAT Only)
This is a flash memory boot mode. See section 17, ROM, for details.
Except for the fact that flash memory programming and erasing can be performed, operation in
this mode is the same as in advanced single chip mode.
3.3.4
Mode 4 (Expanded Mode with On-Chip ROM Disabled)
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Pins P13 to P10, ports A, B, and C function as an address bus, ports D and E functions as a data
bus, and part of port F carries bus control signals.
Pins P13 to P10 function as input ports immediately after a reset. These pins can be set to output
addresse by setting the corresponding data direction register (DDR) bits and A23E to A20E in
PFCR1 to 1.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if
8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.
Rev. 5.00, 12/03, page 75 of 1088
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