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3.3
Operating Mode Descriptions
3.3.1
Mode 4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports 1, A, B, and C, function as an address bus, ports D and E function as a data bus, and part of
port F carries bus control signals.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-
bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.
3.3.2
Mode 5
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports 1, A, B, and C, function as an address bus, ports D and E function as a data bus, and part of
port F carries bus control signals.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16-
bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and
port E becomes a data bus.
3.3.3
Mode 6
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
Ports 1, A, B, and C, function as input port pins immediately after a reset. Address output can be
performed by setting the corresponding DDR (data direction register) bits to 1.
Port D function as a data bus, and part of port F carries data bus signals.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16-
bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and
port E becomes a data bus.
3.3.4
Mode 7
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,
but external addresses cannot be accessed.
All I/O ports are available for use as input-output ports.
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