Interrupt Request; Bit Synchronous Circuit; Table 15.3 Interrupt Requests - Renesas H8 Series Hardware Manual

15.5

Interrupt Request

There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun. Table 15.3 shows the contents of
each interrupt request.

Table 15.3 Interrupt Requests

Interrupt Request
Transmit Data Empty
Transmit End
Receive Data Full
STOP Recognition
NACK Receive
Arbitration
Lost/Overrun
When interrupt conditions described in table 15.3 are 1 and the I bit in CCR is 0, the CPU
executes an interrupt exception processing. Interrupt sources should be cleared in the exception
processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to
ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the
same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive
data of one byte may be transmitted.
15.6

Bit Synchronous Circuit

In master mode,this module has a possibility that high level period may be short in the two states
described below.
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-
up resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 15.21 shows the timing of the bit synchronous circuit and table 15.4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
Abbreviation Interrupt Condition
TXI (TDRE=1)
TEI (TEND=1)
RXI (RDRF=1)
STPI (STOP=1)
NAKI {(NACKF=1)+(AL=1)}
(NAKIE=1)
Section 15 I
2
I
(TIE=1)
•
(TEIE=1)
•
(RIE=1)
•
(STIE=1)
•
•
Rev. 1.00 Aug. 28, 2006 Page 273 of 400
2
C Bus Interface 2 (IIC2)
Clocked
Synchronous
C Mode Mode
×
×
REJ09B0268-0100