Bit Synchronization Circuit - Renesas R8C Series User Manual

R8C/1A Group, R8C/1B Group
16.3.6

Bit Synchronization Circuit

When setting the I
two cases:
• If the SCL signal is driven L level by a slave device
• If the rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line.
Therefore, the SCL signal is monitored and communication is synchronized bit by bit.
Figure 16.45 shows the Timing of Bit Synchronization Circuit and Table 16.8 lists the Time between Changing
SCL Signal from "L" Output to High-Impedance and Monitoring of SCL Signal.
Figure 16.45 Timing of Bit Synchronization Circuit
Table 16.8 Time between Changing SCL Signal from "L" Output to High-Impedance and
Monitoring of SCL Signal
CKS3
0
1
1Tcyc = 1/f1(s)
Rev.1.30 Dec 08, 2006
REJ09B0252-0130
2
C bus interface to master mode, the high-level period may become shorter in the following
Basis clock of SCL
monitor timing
SCL
Internal SCL
ICCR1 Register
CKS2
0
1
0
1
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16. Clock Synchronous Serial Interface
VIH
Time for Monitoring SCL
7.5Tcyc
19.5Tcyc
17.5Tcyc
41.5Tcyc