Motorola MPC860 PowerQUICC User Manual page 80

Part I. Overview
Ñ MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16
virtual address spaces and 16 protection groups
Ñ Advanced on-chip-emulation debug mode
¥ Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
¥ 32 address lines
¥ Complete static design
¥ Memory controller (eight banks)
Ñ Contains complete dynamic RAM (DRAM) controller
Ñ Each bank can be a chip select or RAS to support a DRAM bank
Ñ Up to 30 wait states programmable per memory bank
Ñ Glueless interface to DRAM, SIMMS, SRAM, EPROMs, ßash EPROMs, and
other memory devices.
Ñ DRAM controller programmable to support most size and speed memory
interfaces
Ñ Four CAS lines, four WE lines, one OE line
Ñ Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
Ñ Variable block sizes (32 KbyteÐ256 Mbyte)
Ñ Selectable write protection
Ñ On-chip bus arbitration logic
¥ General-purpose timers
Ñ Four 16-bit timers or two 32-bit timers
Ñ Gate mode can enable/disable counting
Ñ Interrupt can be masked on reference match and event capture
¥ System integration unit (SIU)
Ñ Bus monitor
Ñ Software watchdog
Ñ Periodic interrupt timer (PIT)
Ñ Low-power stop mode
Ñ Clock synthesizer
Ñ PowerPC decrementer and time base
Ñ Real-time clock (RTC)
Ñ Reset controller
Ñ IEEE 1149.1 test access port (JTAG)
1-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA