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Figure
Number
9-16
MMU Tablewalk Special Register (M_TW) ..................................................... 9-24
9-17
IMMU CAM Entry Read Register (MI_CAM) ................................................. 9-25
9-18
IMMU RAM Entry Read Register 0 (MI_RAM0) ............................................ 9-26
9-19
IMMU RAM Entry Read Register 1 (MI_RAM1) ............................................ 9-27
9-20
DMMU CAM Entry Read Register (MD_CAM).............................................. 9-28
9-21
DMMU RAM Entry Read Register 0 (MD_RAM0)......................................... 9-29
9-22
DMMU RAM Entry Read Register 1 (MD_RAM1)......................................... 9-30
9-23
DTLB Reload Code Example ............................................................................ 9-33
9-24
ITLB Reload Code Example.............................................................................. 9-33
9-25
Configuring the TLB Replacement Counter...................................................... 9-34
10-1
Data Cache Load Timing ................................................................................... 10-2
10-2
Writeback Arbitration TimingÑExample 1 ...................................................... 10-2
10-3
Writeback Arbitration TimingÑExample 2 ...................................................... 10-2
10-4
Private Writeback Bus Load Timing ................................................................. 10-3
10-5
External Load Timing ........................................................................................ 10-3
10-6
Full Completion Queue Timing ......................................................................... 10-4
10-7
Branch Folding Timing...................................................................................... 10-5
10-8
Branch Prediction Timing.................................................................................. 10-5
10-9
Bus Latency for String Instructions ................................................................... 10-8
11-1
System Configuration and Protection Logic...................................................... 11-3
11-2
Internal Memory Map Register (IMMR)........................................................... 11-5
11-3
SIU Module Configuration Register (SIUMCR)............................................... 11-6
11-4
System Protection Control Register (SYPCR) .................................................. 11-9
11-5
Transfer Error Status Register (TESR) ............................................................ 11-10
11-6
Register Lock Mechanism ............................................................................... 11-12
11-7
MPC860 Interrupt Structure ............................................................................ 11-13
11-8
SIU Interrupt Processing.................................................................................. 11-15
11-9
IRQ0 Logical Representation .......................................................................... 11-15
11-10
SIU Interrupt Pending Register (SIPEND) ...................................................... 11-17
11-11
SIU Interrupt Mask Register (SIMASK) ......................................................... 11-17
11-12
SIU Interrupt Edge/Level Register (SIEL) ...................................................... 11-18
11-13
SIU Interrupt Vector Register (SIVEC)........................................................... 11-19
11-14
Interrupt Table Handling Example .................................................................. 11-20
11-15
Software Watchdog Timer Service State Diagram.......................................... 11-21
11-16
Software Watchdog Timer Block Diagram ..................................................... 11-22
11-17
Software Service Register (SWSR) ................................................................. 11-22
11-18
Decrementer Register (DEC)........................................................................... 11-24
11-19
Timebase Upper Register (TBU) ..................................................................... 11-24
11-20
Timebase Lower Register (TBL) ..................................................................... 11-25
11-21
Timebase Reference Registers (TBREFA and TBREFB) ............................... 11-25
11-22
Timebase Status and Control Register (TBSCR)............................................. 11-26
11-23
Real-Time Clock Block Diagram .................................................................... 11-27
11-24
Real-Time Clock Status and Control Register (RTCSC) ................................ 11-27
xxxviii
ILLUSTRATIONS
Title
MPC860 PowerQUICC UserÕs Manual
Page
Number
MOTOROLA
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