Organization - Motorola MPC860 PowerQUICC User Manual

Organization

Following is a summary and a brief description of the chapters of this manual:
¥ Part I, ÒOverview,Ó provides a high-level description of the MPC860, describing
general operation and listing basic features.
Ñ Chapter 1, ÒMPC860 Overview, Ó provides a high-level description of MPC860
functions and features. It roughly follows the structure of this book, summarizing
the relevant features and providing references for the reader who needs
additional information.
Ñ Chapter 2, ÒMemory Map,Ó presents a table showing where MPC860 registers
are mapped in memory. It includes cross references that indicate where the
registers are described in detail.
Ñ Chapter 3, ÒHardware Interface Overview,Ó provides an MPC860 pinout
diagram and signal listing.
¥ Part II, ÒPowerPC Microprocessor Module,Ó describes the PowerPC microprocessor
core embedded in the MPC860. These chapters provide details concerning the
processor core as an implementation of the PowerPC architecture.
Ñ Chapter 4, ÒThe PowerPC Core,Ó provides an overview of the MPC860 core,
summarizing topics described in further detail in subsequent chapters in Part II.
Ñ Chapter 5, ÒPowerPC Core Register Set,Ó describes the hardware registers
accessible to the MPC860 core. These include both architecturally-deÞned and
MPC860-speciÞc registers.
Ñ Chapter 6, ÒMPC860 Instruction Set,Ó describes the PowerPC instructions
implemented on the MPC860, including MPC860-speciÞc features.
Ñ Chapter 7, ÒExceptions,Ó describes the PowerPC exception model as it is
implemented on the MPC860.
Ñ Chapter 8, ÒInstruction and Data Caches,Ó describes the organization of the on-
chip instruction and data caches, cache control, various cache operations, and the
interaction between the caches, the load/store unit (LSU), the instruction
sequencer, and the system interface unit (SIU).
Ñ Chapter 9, ÒMemory Management Unit (MMU)Ó describes how the PowerPC
MMU model is implemented on the MPC860. Although the MPC860 MMU is
based on the PowerPC MMU model, it differs greatly in many respects, which
are described in this chapter.
Ñ Chapter 10, ÒInstruction Execution Timing,Ó describes the MPC860 instruction
unit, and provides ways to make greatest advantage of its RISC architecture
characteristics, such as pipelining and parallel execution. It includes a table of
instruction latencies and lists dependencies and potential bottlenecks.
lxiv MPC860 PowerQUICC UserÕs Manual MOTOROLA