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Figure
Number
21-14
One Clock Delay from Sync to Data (xFSD = 01) .......................................... 21-20
21-15
No Delay from Sync to Data (xFSD = 00) ...................................................... 21-20
21-16
Clock Edge (CE) Effect when DSC = 0 .......................................................... 21-21
21-17
Clock Edge (CE) Effect when DSC = 1 .......................................................... 21-21
21-18
Frame Transfers when xFSD = 0 and CE = 1.................................................. 21-22
21-19
CE = 0 and FE Interaction with xFSD = 0....................................................... 21-23
21-20
SI Clock Route Register (SICR) ...................................................................... 21-24
21-21
SI Command Register (SICMR)...................................................................... 21-25
21-22
SI Status Register (SISTR) .............................................................................. 21-25
21-23
SI RAM Pointer Register (SIRP)..................................................................... 21-26
21-24
Dual IDL Bus Application Example................................................................ 21-28
21-25
ISDN Terminal Adaptor Using IDL ................................................................ 21-29
21-26
IDL Bus Signals............................................................................................... 21-30
21-27
GCI Bus Signals............................................................................................... 21-33
21-28
Bank-of-Clocks Selection Logic for NMSI ..................................................... 21-37
21-29
Baud Rate Generator (BRG) Block Diagram .................................................. 21-39
21-30
Baud Rate Generator Configuration Registers (BRGCn)................................ 21-40
22-1
SCC Block Diagram .......................................................................................... 22-2
22-2
GSMR_HÑGeneral SCC Mode Register (High Order) ................................... 22-4
22-3
GSMR_LÑGeneral SCC Mode Register (Low Order)..................................... 22-6
22-4
Data Synchronization Register (DSR) ............................................................. 22-10
22-5
Transmit-on-Demand Register (TODR) .......................................................... 22-10
22-6
SCC Buffer Descriptors (BDs) ........................................................................ 22-12
22-7
SCC BD and Buffer Memory Structure........................................................... 22-13
22-8
Function Code Registers (RFCR and TFCR) .................................................. 22-16
22-9
Output Delay from RTS Asserted for Synchronous Protocols ........................ 22-19
22-10
Output Delay from CTS Asserted for Synchronous Protocols ........................ 22-19
22-11
CTS Lost in Synchronous Protocols ................................................................ 22-20
22-12
Using CD to Control Synchronous Protocol Reception .................................. 22-21
22-13
DPLL Receiver Block Diagram....................................................................... 22-22
22-14
DPLL Transmitter Block Diagram .................................................................. 22-23
22-15
DPLL Encoding Examples .............................................................................. 22-25
23-1
UART Character Format.................................................................................... 23-1
23-2
Two UART Multidrop Configurations .............................................................. 23-7
23-3
Control Character Table, RCCM, and RCCR.................................................... 23-8
23-4
Transmit Out-of-Sequence Register (TOSEQ)................................................ 23-10
23-5
Data Synchronization Register (DSR) ............................................................. 23-11
23-6
Protocol-Specific Mode Register for UART (PSMR) ..................................... 23-13
23-7
SCC UART Receiving using RxBDs .............................................................. 23-16
23-8
SCC UART RxBD........................................................................................... 23-17
23-9
SCC UART Transmit Buffer Descriptor (TxBD)............................................ 23-18
23-10
SCC UART Interrupt Event Example.............................................................. 23-20
23-11
SCC UART Event Register (SCCE) and Mask Register (SCCM) .................. 23-20
xliv
ILLUSTRATIONS
Title
MPC860 PowerQUICC UserÕs Manual
Page
Number
MOTOROLA
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