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Table
Number
6-16
Memory Synchronization InstructionsÑUISA..................................................... 6-18
6-17
Move from Time Base Instruction ........................................................................ 6-20
6-18
Memory Synchronization InstructionsÑVEA ...................................................... 6-20
6-19
User-Level Cache Instructions .............................................................................. 6-22
6-20
System Linkage Instructions ................................................................................. 6-22
6-21
Move to/from Machine State Register Instructions............................................... 6-22
6-22
Move to/from Special-Purpose Register Instructions............................................ 6-23
6-23
Supervisor-Level Cache Management Instruction ................................................ 6-23
6-24
Translation Lookaside Buffer Management Instructions ...................................... 6-24
7-1
Offset of First Instruction by Exception Type......................................................... 7-2
7-2
Instruction-Related Exception Detection Order ...................................................... 7-4
7-3
Exception Priority.................................................................................................... 7-4
7-4
Register Settings after a System Reset Interrupt Exception .................................... 7-5
7-5
Register Settings after a Machine Check Interrupt Exception ................................ 7-6
7-6
Register Settings after an External Interrupt ........................................................... 7-7
7-7
Register Settings after an Alignment Exception ..................................................... 7-8
7-8
Register Settings after a Program Exception........................................................... 7-9
7-9
Register Settings after a Decrementer Exception .................................................. 7-10
7-10
Register Settings after a System Call Exception ................................................... 7-11
7-11
Register Settings after a Trace Exception ............................................................. 7-11
7-12
Register Settings after a Software Emulation Exception ...................................... 7-12
7-13
Register Settings after an Instruction TLB Miss Exception .................................. 7-13
7-14
Register Settings after a Data TLB Miss Exception.............................................. 7-13
7-15
Register Settings after an Instruction TLB Error Exception ................................. 7-14
7-16
Register Settings after a Data TLB Error Exception ............................................. 7-14
7-17
Register Settings after a Debug Exception ............................................................ 7-15
7-18
Additional SPRs that Affect MSR Bits ................................................................. 7-17
7-19
Exception Latency ................................................................................................. 7-19
7-20
Before and After Exceptions ................................................................................. 7-20
8-1
Instruction Cache Control and Status RegisterÑIC_CST ...................................... 8-7
8-2
Instruction Cache Address RegisterÑIC_ADR ...................................................... 8-8
8-3
Instruction Cache Data Port RegisterÑIC_DAT .................................................... 8-8
8-4
IC_ADR Fields for Cache Read Commands........................................................... 8-9
8-5
IC_DAT Format when Reading a Tag .................................................................... 8-9
8-6
Data Cache Control and Status RegisterÑDC_CST............................................. 8-12
8-7
Data Cache Address RegisterÑDC_ADR ............................................................ 8-14
8-8
Data Cache Data Port RegisterÑDC_DAT .......................................................... 8-14
8-9
DC_ADR Fields for Cache Read Commands ....................................................... 8-14
8-10
DC_DAT Format when Reading a Tag................................................................. 8-15
8-11
Copyback Buffer Select Field (DC_CST[21Ð27]) Encoding ................................ 8-15
9-1
Identical Entries Required in Level-One/Level-Two Tables ................................ 9-11
9-2
Number of Replaced EA Bits per Page Size ......................................................... 9-13
9-3
Level-One Segment Descriptor Format................................................................. 9-13
lii
TABLES
Title
MPC860 PowerQUICC UserÕs Manual
Page
Number
MOTOROLA
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