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Figure
Number
11-25
Real-Time Clock Register (RTC) .................................................................... 11-28
11-26
Real-Time Clock Alarm Register (RTCAL).................................................... 11-29
11-27
Real-Time Clock Alarm Seconds Register (RTSEC)...................................... 11-30
11-28
Periodic Interrupt Timer Block Diagram......................................................... 11-31
11-29
Periodic Interrupt Status and Control Register (PISCR) ................................. 11-31
11-30
PIT Count Register (PITC) .............................................................................. 11-32
11-31
PIT Register (PITR)......................................................................................... 11-33
12-1
Power-On and Hard Reset Sequence ................................................................. 12-4
12-2
Soft Reset Sequence........................................................................................... 12-5
12-3
Reset Status Register (RSR) .............................................................................. 12-5
12-4
Data Bus Configuration Input Circuit................................................................ 12-7
12-5
Reset Configuration Sampling for Short PORESET Assertion......................... 12-8
12-6
Reset Configuration Sampling for Long PORESET Assertion ......................... 12-8
12-7
Reset Configuration Sampling Timing Requirements....................................... 12-9
12-8
Hard Reset Configuration Word ........................................................................ 12-9
13-1
MPC860 External Signals.................................................................................. 13-2
13-2
Signals and Pin Numbers (Part 1)...................................................................... 13-3
13-3
Signals and Pin Numbers (Part 2)...................................................................... 13-4
13-4
Three-State Buffers and Active Pull-Up Buffers............................................. 13-21
14-1
Input Sample Window ....................................................................................... 14-2
14-2
MPC860 Bus Signals ......................................................................................... 14-3
14-3
Basic Transfer Protocol...................................................................................... 14-6
14-4
Basic Flow Diagram of a Single-Beat Read Cycle............................................ 14-7
14-5
Single-Beat Read CycleÐBasic TimingÐZero Wait States................................. 14-8
14-6
Basic Timing: Single-Beat Read Cycle, One Wait State................................... 14-9
14-7
Basic Flow of a Single-Beat Write Cycle ........................................................ 14-10
14-8
Basic Timing: Single-Beat Write Cycle, Zero Wait States.............................. 14-11
14-9
Basic Timing: Single-Beat Write Cycle, One Wait State ................................ 14-12
14-10
Basic Timing: Single-Beat, 32-Bit Data Write Cycle, 16-Bit Port Size.......... 14-13
14-11
Basic Flow of a Burst-Read Cycle................................................................... 14-16
14-12
Burst-Read Cycle: 32-Bit Port Size, Zero Wait State...................................... 14-17
14-13
Burst-Read CycleÐ32-Bit Port SizeÐOne Wait State....................................... 14-18
14-14
Burst-Read CycleÐ32-Bit Port SizeÐWait States between Beats..................... 14-19
14-15
Burst-Read Cycle: One Wait State between Beats (16-Bit Port Size)............. 14-20
14-16
Basic Flow of a Burst Write Cycle .................................................................. 14-21
14-17
Burst-Write CycleÐ32-Bit Port SizeÐZero Wait States ................................... 14-22
14-18
Burst-Inhibit CycleÐ32-Bit Port Size............................................................... 14-23
14-19
Internal Operand Representation ..................................................................... 14-24
14-20
Interface to Different Port Size Devices .......................................................... 14-24
14-21
Bus Arbitration Flowchart ............................................................................... 14-26
14-22
Masters Signals Basic Connection................................................................... 14-27
14-23
Bus Arbitration Timing Diagram..................................................................... 14-28
14-24
Internal Bus Arbitration State Machine ........................................................... 14-29
MOTOROLA
ILLUSTRATIONS
Title
Illustrations
Page
Number
xxxix
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