Misalign Access Timing; Misalign Access Timing - Renesas NU85E Preliminary User's Manual

4.9.7 Misalign access timing

The VSB access timing when misalign access is enabled (when a high level is input to the IFIMAEN pin) is shown
below.
VBCLK (Input)
VMTTYP1, VMTTYP0
(Output)
VMLOCK (Output)
VMA27 to VMA0 (Output)
VMWRITE (Output)
VMBENZ3 to VMBENZ0
(Output)
VMCTYP2 to VMCTYP0
(Output)
VMSEQ2 to VMSEQ0
(Output)
VMSIZE1, VMSIZE0
(Output)
VMSTZ (Output)
VDCSZ7 to VDCSZ0
(Output)
VBDI31 to VBDI0
(Input)
VBDO31 to VBDO0
(Output)
VMWAIT (Input)
VMAHLD (Input)
VMLAST (Input)
Remarks 1. O mark: Sampling timing
:
2. The timing seen from the NU85E when the NU85E has the bus access right is shown.
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CHAPTER 4 BCU
Figure 4-18. Misalign Access Timing (1/2)
(a) Timing for access to even addresses
(Writing the 32-bit data "12345678H" to address "200002H")
Halfword write
(1,0)
200002H
H
(0,0,1,1)
L
56780000H
Arbitrary input level
Preliminary User's Manual A14874EJ3V0UM
Halfword write
(1,1) (1,0)
200004H
(0,1,0)
(0,0,0)
(0,1)
(1,1)
(1,1,0,0)
00001234H