12.5.10 Interrupt Priority Level Select Circuit - Renesas M16C/62P Series Hardware Manual

M16C/62P Group (M16C/62P, M16C/62PT)

12.5.10 Interrupt Priority Level Select Circuit

The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt
requests are sampled at the same sampling point.
Figure 12.10 shows the Interrupts Priority Select Circuit.
Priority level of each interrupt
INT1
Timer B2
Timer B0
Timer A3
Timer A1
Timer B4, UART1 bus collision
INT3
INT2
INT0
Timer B1
Timer A4
Timer A2
Timer B3, UART0 bus collision
Timer B5
UART1 reception, ACK1
UART0 reception, ACK0
UART2 reception, ACK2
A/D conversion
DMA1
UART 2 bus collision
SI/O4, INT5
Timer A0
UART1 transmission, NACK1
UART0 transmission, NACK0
UART2 transmission, NACK2
Key input interrupt
DMA0
SI/O, INT4
IPL
I flag
Address match
Watchdog timer
Oscillation stop and
re-oscillation detection
Low voltage detection
DBC
NMI
Figure 12.10 Interrupts Priority Select Circuit
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Level 0 (initial value)
Highest
Priority of peripheral function interrupts
(if priority levels are same)
Lowest
Page 119 of 390
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Interrupt request level resolution output to clock
generating circuit (Figure 10.1 Clock Generation Circuit)
Interrupt request
accepted
010-62245566 13810019655
12. Interrupt