Figure 7.34 Example Of Transfer In Single Address Mode (Byte Write) - Renesas H8SX/1500 Series Hardware Manual

Section 7 DMA Controller (DMAC)
(2)
Single Address Mode (Write and Cycle Stealing)
In single address mode, data of one byte, one word, or one longword is transferred at a single
transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the
CPU are executed in the bus released cycles.
In figure 7.34, the TEND signal output is enabled and data is transferred in bytes from the external
8-bit 2-state access space to the external device in single address mode (write).
Bφ
Address bus
HHWR, HLWR
LLWR
DACK
TEND
Bus
released

Figure 7.34 Example of Transfer in Single Address Mode (Byte Write)

Rev. 3.00 Mar. 14, 2006 Page 192 of 804
REJ09B0104-0300
DMA write
DMA write
cycle
cycle
Bus
released
DMA write
cycle
Bus
Bus
released
released
DMA write
cycle
Bus
Last transfer
released
cycle