Figure 25.19 Burst Mpx-Io Interface Bus Cycle Single Read Write (One Address Cycle, One Software Wait) - Renesas HD6417641 Hardware Manual

CKIO
A25 to A0
t
CS6B
t
RD/WR
t
FRAME
Read D31 to D0
t
Write D31 to D0
t
BS
t
DACKn,
TENDn*
WAIT
RD
WEn
Note: * Waveform for DACKn and TENDn when active low is selected.
Figure 25.19 Burst MPX-IO Interface Bus Cycle Single Read Write
(One Address Cycle, One Software Wait)
Tm1 Tmd1w
t
AD1
CSD1
RWD1
t
FMD
FMD
t
t
WDD1
WDH1
t
WDD1
t
WDD1
WDH1
t
BSD
BSD
DACD
t
WTH1
t
WTS1
Section 25 Electrical Characteristics
Tmd1
t
AD1
t
CSD1
t
RWD1
t
FMD
t
RDS2
t
RDH2
t
WDH1
t
DACD
Rev. 4.00 Sep. 14, 2005 Page 931 of 982
REJ09B0023-0400