Table 18.31 Pwm Output Registers And Output Pins - Renesas HD6417641 Hardware Manual

The correspondence between PWM output pins and registers is shown in table 18.31.

Table 18.31 PWM Output Registers and Output Pins

Channel
0
1
2
3
4
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
Registers
TGRA_0
TGRB_0
TGRC_0
TGRD_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
TGRA_3
TGRB_3
TGRC_3
TGRD_3
TGRA_4
TGRB_4
TGRC_4
TGRD_4
Section 18 Multi-Function Timer Pulse Unit (MTU)
Output Pins
PWM Mode 1
TIOC0A
TIOC0C
TIOC1A
TIOC2A
TIOC3A
TIOC3C
TIOC4A
TIOC4C
Rev. 4.00 Sep. 14, 2005 Page 577 of 982
PWM Mode 2
TIOC0A
TIOC0B
TIOC0C
TIOC0D
TIOC1A
TIOC1B
TIOC2A
TIOC2B
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
REJ09B0023-0400