Motorola PowerQUICC II MPC8280 Series Reference Manual page 964

Channel-Specific Parameters
29.3.4.3.1 AERM Implementation
The SS7 microcode implements the ITU Q.703 alignment error rate monitor (AERM). The
microcode uses the T, SUERM, M and M_cnt parameters. The M_cnt parameter is
incremented for every T errored frames. If M_cnt reaches M, an AERM interrupt is
generated to layer 3.
Note that in AERM mode no SUERM interrupt is generated. Also, the algorithm associated
with D and D_cnt is disabled as per the ITU specification.
29.3.4.3.2 AERM in Japanese SS7
To meet the Japanese AERM requirements the user must change the parameters T and D.
Note that the interrupt generated is not AERM but SUERM.
During proving, do the following:
1. Set SS7_OPT register to 0b0000 001X XX00 XXXX. The value of X doesn't matter
because these bits do not affect the operation of the error counter.
2. Clear JTRdelay parameter to'0.'
3. Set parameters T (threshold) and D (up counter) to'1.'
4. Clear parameter SUERM (error counter) to'0.'
5. Set JTTDelay to value required to generate 24ms delay.
These settings allow FISU or LSSU transmission to be delayed by the required 24ms
(JTTDelay). They also allow the correct operation of the JT Q703 error counter and ensure
that an SUERM interrupt is generated on the first SU received in error.
After proving period, set the parameters (T and D) to values according to the Japanese
SUERM. See section Table 29-12.
To disable AERM and enter SUERM, do the following:
1. Set SUERM_DIS bit in SS7_OPT.
2. Set parameters (T, D & SUERM) for Japanese SUERM.
3. Clear SUERM_DIS bit in SS7_OPT.
29.3.4.3.3 Disabling SUERM
When SS7_OPT[SUERM_DIS] is set, the N_cnt and D_cnt parameters are not
decremented by the microcode and no SUERM interrupt is generated. This allows these
parameters to be updated, for example, at the end of the proving period in alignment error
monitoring.
Note: If the SS7 controller is in the octet counting mode (OCM) when SUERM_DIS is set,
then if no idles (only flags/data) are received while SUERM_DIS is set, then after the host
29-26
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MPC8280 PowerQUICC II Family Reference Manual
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