Motorola PowerQUICC II MPC8280 Series Reference Manual page 803

Table 23-10 describes PSMR fields.
Bits Name
0–3 NOS Minimum number of SYN1–SYN2 pairs (defined in DSR) sent between or before messages.If NOS
= 0000, one pair is sent. If NOS = 1111, 16 pairs are sent. The entire pair is always sent, regardless
of how GSMR[SYNL) is set. NOS can be modified on-the-fly.
4–5 CRC CRC selection.
x0 Reserved.
01 CRC16 (BISYNC). X16 + X15 + X2 + 1. PRCRC and PTCRC should be initialized to all zeros or
all ones before the channel is enabled. In either case, the transmitter sends the calculated CRC
noninverted and the receiver checks the CRC against zero. Eight-bit data characters (without
parity) are configured when CRC16 is chosen.
11 LRC (sum check). (BISYNC). For even LRC, initialize PRCRC and PTCRC to zeros before the
channel is enabled; for odd LRC, they should be initialized to ones.
Note that the receiver checks character parity when BCS is programmed to LRC and the receiver
is not in transparent mode. The transmitter sends character parity when BCS is programmed to
LRC and the transmitter is not in transparent mode. Use of parity in BISYNC assumes that 7-bit
data characters are being used.
6 RBCS Receive BCS. The receiver internally stores two BCS calculations separated by an eight serial clock
delay to allow examination of a received byte to determine whether it should used in BCS calculation.
0 Disable receive BCS.
1 Enable receive BCS. Should be set (or reset) within the time taken to receive the following data
byte. When RBCS is reset, BCS calculations exclude the latest fully received data byte. When
RBCS is set, BCS calculations continue as normal.
7 RTR Receiver transparent mode.
0 Normal receiver mode with SYNC stripping and control character recognition.
1 Transparent receiver mode. SYNCs, DLEs, and control characters are recognized only after a
leading DLE character. The receiver calculates the CRC16 sequence even if it is programmed to
LRC while in transparent mode. Initialize PRCRC to the CRC16 preset value before setting RTR.
8 RVD Reverse data.
0 Normal operation.
1 Any portion of this SCC defined to operate in BISYNC mode operates by reversing the character
bit order and sending the msb first.
9 DRT Disable receiver while sending. DRT should not be set for typical BISYNC operation.
0 Normal operation.
1 As the SCC sends data, the receiver is disabled and gated by the internal RTS signal. This helps
if the BISYNC channel is being configured onto a multidrop line and the user does not want to
receive its own transmission. Although BISYNC usually uses a half-duplex protocol, the receiver
is not actually disabled during transmission.
Note: If DRT = 1, GSMR_H[CDS] should be cleared unless both of the following are true: the same
clock is used for TCLK and RCLK, and CTS either has synchronous timing or is always asserted.
10–11 — Reserved, should be cleared.
MOTOROLA
Freescale Semiconductor, Inc.
Table 23-10. PSMR Field Descriptions
Chapter 23. SCC BISYNC Mode
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BISYNC Mode Register (PSMR)
Description
23-11