Motorola PowerQUICC II MPC8280 Series Reference Manual page 920

SMC in UART Mode
9-bit data fields occupy three half words in memory (the 9 least-significant bits of each half
word).
Tx data buffer pointer points to the first location of the buffer. It can be even or odd, unless
the number of data bits in the UART character is greater than 8 bits. Then the buffer pointer
must be even. For instance, the pointer to 8-bit data, 1 start, and 1 stop characters can be
even or odd, but the pointer to 9-bit data, 1 start, and 1 stop characters must be even. The
buffer can reside in internal or external memory.
28.3.11 SMC UART Event Register (SMCE)/Mask Register
(SMCM)
The SMC event register (SMCE) generates interrupts and report events recognized by the
SMC UART channel. When an event is recognized, the SMC UART controller sets the
corresponding SMCE bit. Bits are cleared by writing a 1; writing 0 has no effect. The SMC
mask register (SMCM) has the same bit format as SMCE. Setting an SMCM bit enables,
and clearing it disables, the corresponding interrupt. All unmasked bits must be cleared
before the CP clears the internal interrupt request. Figure 28-9 represents the
SMCE/SMCM registers.
0
Field — BRKE
Reset
R/W
Addr 0x11A86 (SMCE1), 0x11A96 (SMCE2)/ 0x11A8A (SMCM1), 0x11A9A (SMCM2)
Figure 28-9. SMC UART Event Register (SMCE)/Mask Register (SMCM)
Table 28-9 describes SMCE/SMCM fields.
Table 28-9. SMCE/SMCM Field Descriptions
Bits Name
0 — Reserved, should be cleared.
1 BRKE Break end. Set no sooner than after one idle bit is received after the break sequence.
2 — Reserved, should be cleared.
3 BRK Break character received. Set when a break character is received. If a very long break sequence
occurs, this interrupt occurs only once after the first all-zeros character is received.
4 — Reserved, should be cleared.
5 BSY Busy condition. Set when a character is received and discarded due to a lack of buffers. Set no
sooner than the middle of the last stop bit of the first receive character for which there is no available
buffer. Reception resumes when an empty buffer is provided.
28-20
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1 2 3
— BRK
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4 5
— BSY
0
R/W
Description
6 7
TXB RXB
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