Motorola PowerQUICC II MPC8280 Series Reference Manual page 1089

Table 31-35 describes AAL5 RxBD fields.
m
Offset Bits Name
0x00 0 E
1 —
2 W
3 I
4 L
5 F
6 CM
7–9 —
10 CLP
11 CNG
12 ABRT
13 CPUU
14 LNE
15 CRE
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
Freescale Semiconductor, Inc.
Table 31-35. AAL5 RxBD Field Descriptions
Empty.
0 The buffer associated with this RxBD is full or data reception was aborted due to an
error. The core can read or write any fields of this RxBD. The CP does not use this
BD again while E remains zero.
1 The buffer associated with this RxBD is empty or reception is in progress. This RxBD
and its receive buffer are controlled by the CP. Once E is set, the core should not
write any fields of this RxBD.
Reserved, should be cleared.
Wrap (final BD in table)
0 This is not the last BD in the RxBD table of the current channel.
1 This is the last BD in the RxBD table of this current channel. After this buffer has been
used, the CP receives incoming data into the first BD in the table. The number of
RxBDs in this table is programmable and is determined only by the W bit. The current
table cannot exceed 64 Kbytes.
Interrupt
0 No interrupt is generated after this buffer has been used.
1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this
buffer. FCCE[GINTx] is set in the event register when INT_CNT reaches the global
interrupt threshold.
Last in frame. Set by the ATM controller for the last buffer in a frame.
0 Buffer is not last in a frame.
1 Buffer is last in a frame. ATM controller writes frame length in DL and updates the
error flags.
First in frame. Set by the ATM controller for the first buffer in a frame.
0 The buffer is not the first in a frame.
1 The buffer is the first in a frame.
Continuous mode
0 Normal operation.
1 The CP does not clear the empty bit after this BD is closed, allowing the associated
buffer to be overwritten automatically when the CP next accesses this BD.
Reserved, should be cleared.
Cell loss priority. At least one cell associated with the current message was received
with CLP = 1. May be set at the last buffer of the message.
Congestion indication. The last cell associated with the current message was received
with PTI middle bit set. CNG may be set at the last buffer of the message.
Abort message indication. The current message was received with Length field zero.
CPCS-UU+CPI indication. Set when the CPCS-UU+CPI field is non zero. CPUU may
be set at the last buffer of the message.
Rx length error. AAL5 CPCS-PDU length violation. May be set only for the last BD of
the frame if the pad length is greater than 47 or less than zero octets.
Rx CRC error. Indicates CRC32 error in the current AAL5 PDU. Set only for the last BD
of the frame.
For More Information On This Product,
Go to: www.freescale.com
ATM Memory Structure
Description
31-75