Motorola PowerQUICC II MPC8280 Series Reference Manual page 1376

SPI Master Programming Example
Table 39-9. SPI TxBD Status and Control Field Descriptions (continued)
Bits Name
6 CM Continuous mode. Valid only when the SPI is in master mode. In slave mode, it should be cleared.
0 Normal operation.
1 The CP does not clear TxBD[R] after this BD is closed, allowing the buffer to be resent
automatically when the CP next accesses this BD.
7–13 — Reserved, should be cleared.
14 UN Underrun. Indicates that the SPI encountered a transmitter underrun condition while sending the
buffer. This error occurs only when the SPI is in slave mode. The SPI updates UN after it sends the
buffer.
15 ME Multimaster error. Indicates that this buffer is closed because SPISEL was asserted when the SPI
was in master mode. A synchronization problem occurred between devices on the SPI bus. The SPI
updates ME after sending the buffer.
39.8 SPI Master Programming Example
The following sequence initializes the SPI to run at a high speed in master mode:
1. Configure port D to enable SPIMISO, SPIMOSI, SPICLK and SPISEL.
2. Configure a parallel I/O signal to operate as the SPI select output signal if needed.
3. In address 0x89FC, assign a pointer to the SPI parameter RAM.
4. Write RBASE and TBASE in the SPI parameter RAM to point to the RxBD and
TxBD tables in the dual-port RAM. Assuming one RxBD followed by one TxBD at
the beginning of the dual-port RAM, write RBASE with 0x0000 and TBASE with
0x0008.
5. Write RFCR and TFCR with 0x10 for normal operation.
6. Write MRBLR with the maximum number of bytes per Rx buffer. For this case,
assume 16 bytes, so MRBLR = 0x0010.
7. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory.
Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length]
(optional), and 0x0000_1000 to RxBD[Buffer Pointer].
8. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and
contains five 8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005
to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer].
9. Execute the
INIT RX AND TX PARAMETERS
CPCR.
10. Write 0xFF to SPIE to clear any previous events.
11. Write 0x37 to SPIM to enable all possible SPI interrupts.
12. Write 0x0370 to SPMODE to enable normal operation (not loopback), master
mode, SPI enabled, 8-bit characters, and the fastest speed possible.
13. Set SPCOM[STR] to start the transfer.
39-18
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MPC8280 PowerQUICC II Family Reference Manual
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