Motorola PowerQUICC II MPC8280 Series Reference Manual page 1405

Table 41-5. Port A—Dedicated Pin Assignment (PPARA = 1) (continued)
Pin
PDIRA = 1 (Output)
PA12
PA11
PA10
PA9 SMC2: SMTXD
PA8 FCC2: TxAddr[4]
PA7 FCC2: TxAddr[3]
PA6 FCC2: RxAddr[3]
PA5 SCC2: RSTRT
PA4 FCC2: RxAddr[1]
MPHY master
PA3 FCC2: RxAddr[0]
MPHY master
PA2 FCC2: TxAddr[0]
MPHY master
PA1 FCC2: TxAddr[1]
MPHY master
PA0 SCC1: RSTRT
1
Not available on the MPC8270.
2
MSNUM[0–4] is the sub-block code of the peripheral controller using SDMA; MSNUM[5] indicates which section,
transmit or receive, is active during the transfer. See Section 19.2.4, "SDMA Transfer Error MSNUM Registers
(PDTEM and LDTEM)."
MOTOROLA
Freescale Semiconductor, Inc.
Pin Function
PSORA = 0
Default
PDIRA = 0 (Input)
Input
1
FCC1: RxD[2] GND
UTOPIA 8
1
FCC1: RxD[10]
UTOPIA 16
1
FCC1: RxD[1] GND
UTOPIA 8
1
FCC1: RxD[9]
UTOPIA 16
1
FCC1: RxD[0] GND
UTOPIA 8
1
FCC1: RxD[8]
UTOPIA 16
SMC2: SMRXD by PD4
(primary option)
SMC2: SMSYN by PC0
(primary option)
1
FCC1: RxPrty GND
UTOPIA
(secondary option)
1
SCC2: REJECT VDD
1
CLK19 GND
1
CLK20 GND
1
SCC1: REJECT VDD
Chapter 41. Parallel I/O Ports
For More Information On This Product,
Go to: www.freescale.com
PSORA = 1
PDIRA = 0 (Input, or
PDIRA = 1 (Output)
Inout if Specified)
2
MSNUM[3]
2
MSNUM[4]
2
MSNUM[5]
TDM_A1: L1TXD[0] TDM_A1: L1TXD
Output, nibble Inout, serial
TDM_A1: L1RXD[0]
Input, nibble
TDM_A1: L1RXD
Inout, serial
L1TSYNC/GRANT
TDM_A1: L1RSYNC
1
FCC2: RxAddr[2] IDMA4: DREQ
MPHY master
IDMA4: DONE
IDMA4: DACK TDM_A2: L1RXD[1]
IDMA3: DACK
IDMA3: DONE
1
FCC2: TxAddr[2] IDMA3: DREQ
MPHY master
Ports Tables
Default
Input
GND
GND
TDM_A1: GND
GND
GND
VDD
Inout
GND
Nibble
VDD
Inout
GND
41-11