Motorola PowerQUICC II MPC8280 Series Reference Manual page 1438

Branch processing unit, 2-6
BRGCLK, 40-2
BRn (base registers), 11-14
BSYNC (BISYNC SYNC) register, 23-7
BUFCMD (external address and command buffers),
11-45
Buffer
SPI buffer descriptor ring, 27-23
SPI receive buffer descriptor, 27-26
Buffer descriptors
ATM controller
receive, 31-70, 31-74
transmit, 31-69, 31-79
BISYNC mode, 23-12
definition, 32-24
fast communications controllers (FCCs)
Fast Ethernet mode
receive, 36-25
transmit, 36-28
HDLC mode
receive, 37-9
transmit, 37-12
overview
receive, 30-10
transmit, 30-10
GCI mode
monitor channel, 28-35
HDLC mode, 22-9
2
I C controller
receive, 40-13
transmit, 40-14
IDMA emulation
auto buffer, 19-17
IDMA buffers, 19-25
multi-channel controllers (MCCs)
receive, 29-45
transmit, 29-47
overview, 20-11, 32-38
serial management controllers (SMCs), 28-5
serial peripheral interface (SPI)
receive, 39-16
transmit, 39-17
transparent mode
serial communications controllers (SCCs), 24-9
serial management controllers (SMCs), 28-28
UART mode
serial communications controllers (SCCs), 21-16
serial management controllers (SMCs), 28-15
Buffers
BUFCMD, 11-45
Bus interface
hierarchical bus interface example, 11-106
BxTx (byte-select signals), 11-79
Byte stuffing, 23-1
Index-4
Freescale Semiconductor, Inc.
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
Byte-select signals, 11-79
C
Cache units, 2-9
Cascaded mode, 18-3
CHAMR (channel mode register), 29-9
CHAMR (channel mode register, transparent mode),
29-13, 29-16
Chip-select
assertion timing, 11-57
chip-select machine, 11-55
signals, 11-78
write enable deassertion timing, 11-58
clock control,, 10-6, 10-7
Clocks
memory map, 3-8
overview, 10-1
clocks and power control
PLL pins,, 10-5
PLL, low power, and reset control register,, 10-6,
10-7
system clock control,, 10-6
system PLL
skew elimination,, 10-2
clocks and reset keys memory map,, 3-5
CMXFCR (CMX FCC clock route register), 16-13
CMXSCR (CMX SCC clock route register), 16-16
CMXSI1CR (CMX SI1 clock route register), 16-11
CMXSI2CR (CMX SI2 clock route register), 16-12
CMXSMR (CMX SMC clock route register), 16-19
CMXUAR (CMX UTOPIA address register), 16-7
Commands
command, 31-95
ATM TRANSMIT
fast communications controllers (FCCs)
Ethernet mode
receive commands, 36-14
transmit commands, 36-13
HDLC mode
receive commands, 37-6
transmit commands, 37-6
2
I C controller, 40-12
IDMA emulation, 19-28
serial peripheral interface (SPI), 39-14
communication processor module
features, 35-8
Communications processor (CP)
block diagram, 14-6
execution from RAM, 14-8
features list, 14-4
memory map, 3-17
microcode execution from RAM, 14-8
microcode revision number, 14-11
peripheral interface, 14-7
MOTOROLA