Motorola PowerQUICC II MPC8280 Series Reference Manual page 822

SCC Transparent Receive Buffer Descriptor (RxBD)
Table 24-7 describes RxBD status and control fields.
Table 24-7. SCC Transparent RxBD Status and Control Field Descriptions
Bits Name
0 E Empty.
0 The buffer is full or stopped receiving data because an error occurred. The core can read or write
to any fields of this RxBD. The CPM does not use this BD when RxBD[E] is zero.
1 The buffer is not full. This RxBD and buffer are owned by the CPM. Once E is set, the core should
not write any fields of this RxBD.
1 — Reserved, should be cleared.
2 W Wrap (final BD in table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CPM receives data into the first BD that RBASE
points to. The number of BDs in this table is determined only by RxBD[W] and overall space
constraints of the dual-port RAM.
3 I Interrupt.
0 No interrupt is generated after this buffer is used.
1 When this buffer is closed by the transparent controller, the SCCE[RXB] is set. SCCE[RXB] can
cause an interrupt if it is enabled.
4 L Last in frame. Set by the transparent controller when this buffer is the last in a frame, which occurs
when CD is negated (if GSMR_H[CDP] = 0) or an error is received. If an error is received, one or
more of RxBD[OV, CD, DE] are set. Note that the SCC transparent controller writes the number of
buffer (not frame) octets to the last BD's data length field.
0 Not the last buffer in a frame.
1 Last buffer in a frame.
5 F First in frame. The transparent controller sets F when this buffer is the first in the frame:
0 Not the first buffer in a frame.
1 First buffer in a frame.
6 CM Continuous mode.
0 Normal operation.
1 The CPM does not clear RxBD[E] after this BD is closed, letting the buffer be overwritten when
the CPM next accesses this BD. However, RxBD[E] is cleared if an error occurs during reception,
regardless of how CM is set.
7 — Reserved, should be cleared.
8 DE DPLL error. Set by the transparent controller when a DPLL error occurs as this buffer is received. In
decoding modes, where a transition is promised every bit, DE is set when a missing transition
occurs. If a DPLL error occurs, no other error checking is performed.
9–10 — Reserved, should be cleared.
11 NO Rx non-octet. Set when a frame containing a number of bits not exactly divisible by eight is received.
12 — Reserved, should be cleared.
13 CR CRC error indication bits. Indicates that this frame contains a CRC error. The received CRC bytes
are always written to the receive buffer. CRC checking cannot be disabled, but it can be ignored.
14 OV Overrun. Indicates that a receiver overrun occurred during buffer reception.
15 CD Carrier detect lost. Indicates when CD is negated during buffer reception.
Data length and buffer pointer fields are described in Section 20.2, "SCC Buffer
Descriptors (BDs)." The Rx buffer pointer must be divisible by four, unless
24-10
Freescale Semiconductor, Inc.
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
Description
MOTOROLA