Motorola PowerQUICC II MPC8280 Series Reference Manual page 1383

strictly for timing and can be left uninitialized. Configure suitable receive buffers and BDs
to receive the slave's transmission.
If the MPC8280 is the slave target of the read, prepare the I
activate it by setting I2COM[STR]. Figure 40-5 shows the timing for a master read.
SDA
Note: After the nth data byte, the master does not acknowledge the slave.
A master read occurs as follows:
1. Set the master's I2COM[STR] to initiate the read. The transfer starts when the
SDMA channel loads the transmit FIFO with data and the I
2. The slave detects a start condition on SDA and SCL.
3. After the first byte is shifted in, the slave compares the received data to its slave
address. If the slave is an MPC8280, the address is programmed in its I
register (I2ADD).
— If a match is found, the slave acknowledges the received byte and begins
transmitting on the clock pulse immediately following the acknowledge.
— If a match is found but the slave is not ready, the read request is not
acknowledged and the transaction is aborted. If the slave is an MPC8280, a
maskable transmission error interrupt is triggered to allow software to prepare
data for transmission on the next try.
— If a mismatch occurs, the slave ignores the message and searches for a new start
condition.
4. The master acknowledges each byte sent as long as an overrun does not occur. If
the master receiver fails to acknowledge a byte, the slave aborts transmission. For a
slave MPC8280, the abort generates a maskable interrupt. A maskable interrupt is
also issued after a complete buffer is sent or after an error. If an underrun occurs,
the MPC8280 slave sends ones until a stop condition is detected.
40.3.4 I C Multi-Master Considerations
2
The I 2 C controller supports a multi-master configuration, in which the I
alternate between master and slave modes. The I
implementing I 2 C master arbitration in hardware. However, due to the nature of the I
and the implementation of the I
MOTOROLA
Freescale Semiconductor, Inc.
S
T
A
R
T
Device Address
2
Figure 40-5. I C Master Read Timing
2 C controller, certain software considerations must be made.
2
Chapter 40. I
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2 C transmit buffers and BDs and
A
C
K
R
Data Byte
2
2 C controller supports this by
C Controller
2
I C Controller Transfers
N
O
S
A
T
C
O
K
P
C bus is not busy.
2 C address
2 C controller must
2 C bus
40-5