Motorola PowerQUICC II MPC8280 Series Reference Manual page 1250

IMA Programming Model
Table 34-15. IMA Link Transmit Table Entry (continued)
Offset Name
0x0C ITQFP
0x0E ITQXP
0x10 ITINTMSK
0x11 ITINTSTAT
0x12 LSHC
1
Boldfaced entries indicate parameters that must be initialized by the user. All other parameters are
managed by the microcode and should be initialized to zero unless otherwise stated.
34.4.5.1.1 IMA Link Transmit Control (ILTCNTL)
The fields of the ILTCNTL register are shown in Figure 34-21.
0
field TRL
Figure 34-21. IMA Link Transmit Control (ILTCNTL)
Table 34-16 describes the ILTCNTL bit fields.
Bits Name
0 TRL Defines this link as the timing reference link (TRL) of the group.
0 This link is not the TRL.
1 This link is the TRL.
Note: One and only one link of the group must be programmed as the TRL. If zero or more than
one links are defined as TRL, erratic operation will occur.
1 SES Severely errored seconds. Set by software when a severely errored second indication is
detected. When set, causes the transmit stuff event counter to stop counting.
2 — Reserved, initialize to zero.
34-40
Freescale Semiconductor, Inc.
Width
Hword IMA link transmit queue fill pointer. This parameter forms bits 12-27 of
the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are zero.
Initialize this to the value of ITQSP. Refer to Section 34.4.6.1, "Transmit
Queues".
Hword IMA link transmit queue extract pointer. This parameter forms bits
12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31
are zero. Initialize this to the value of ITQSP. Refer to Section 34.4.6.1,
"Transmit Queues".
Byte IMA transmit interrupt mask. Has the same format as the upper byte of
the IMA interrupt queue entry. Setting a bit enables the associated
interrupt; clearing a bit masks it.
For group-related events, only the mask register for the TRL is
referenced.
Byte IMA transmit interrupt status. Indicates the status of transmit interrupt
events.
Byte Stuff holdoff counter. Maintains the minimum five-frame spacing
between stuff events for non-TRL links. Must be initialized to zero. Set
to 4 by the microcode after a stuff event, and decrements after each
ICP cell is sent (saturating at zero). Signalling of 'imminent stuff' (and
subsequent stuff events) will not occur while this counter is non-zero.
1 2
SES —
Table 34-16. ILTCNTL Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
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Description
3 4 5
TXSC
Description
1
7
IGNUM
MOTOROLA