Motorola PowerQUICC II MPC8280 Series Reference Manual page 670

General-Purpose Timer Units
TRR, TCR, TCN connected to D[0–15]
TRR, TCR, TCN connected to D[0–15]
Figure 18-2. Timer Cascaded Mode Block Diagram
If TGCR[CAS] = 1, the two timers function as a 32-bit timer with a 32-bit TRR, TCR, and
TCN. In this case, TMR1 and/or TMR3 are ignored, and the modes are defined using TMR2
and/or TMR4. The capture is controlled from TIN2 or TIN4 and the interrupts are generated
from TER2 or TER4. In cascaded mode, the combined TRR, TCR, and TCN must be
referenced with 32-bit bus cycles.
18.2.2 Timer Global Configuration Registers (TGCR1 and
TGCR2)
The timer global configuration registers (TGCR1 and TGCR2), shown in Figure 18-3 and
Figure 18-4, contain configuration parameters used by the timers. These registers allow
simultaneous starting and stopping of a pair of timers (1 and 2 or 3 and 4) if one bus cycle
is used.
0
Field CAS2
Reset
R/W
Addr
Figure 18-3. Timer Global Configuration Register 1 (TGCR1)
Table 18-1 describes TGCR1 fields.
Bits Name
0 CAS2 Cascade timers.
0 Normal operation.
1 Timers 1 and 2 cascade to form a 32-bit timer.
1 — Reserved, should be cleared.
18-4
Freescale Semiconductor, Inc.
Timer1
Capture
Timer3
Capture
1 2 3
— STP2 RST2
Table 18-1. TGCR1 Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
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Timer2
TRR, TCR, TCN connected to D[16–31]
Timer4
TRR, TCR, TCN connected to D[16–31]
4 5
GM1 —
0000_0000
R/W
0x10D80
Description
Clock
Clock
6 7
STP1 RST1
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