Motorola PowerQUICC II MPC8280 Series Reference Manual page 1313

Freescale Semiconductor, Inc.
Ethernet Channel Frame Reception
became negated). In the fast ethernet transmitter, if CRS is asserted and then negated within
10 clocks after TXEN is negated, the next frame is not deferred and a defer indication is
asserted.
If a collision occurs during the transmit frame, the Ethernet controller follows a specified
backoff procedure and tries to retransmit the frame until the retry limit is reached. The
Ethernet controller stores at least the first 64 bytes of data of the transmit frame in the FCC
FIFO, so that the data does not have to be retrieved from system memory in case of a
collision. This improves bus usage and latency if the backoff timer output requires an
immediate retransmission.
When the end of the current buffer is reached and TxBD[L] = 1, the FCS (32-bit CRC) bytes
are appended (if TxBD[TC] = 1), and TX_EN is negated. This notifies the PHY of the need
to generate the illegal Manchester encoding that signifies the end of an Ethernet frame.
Following the transmission of the FCS, the Ethernet controller writes the frame status bits
into the BD and clears TxBD[R]. When the end of the current buffer is reached and
TxBD[L] = 0 (a frame is comprised of multiple buffers), only TxBD[R] is cleared.
For both half- and full-duplex modes, an interrupt can be issued depending on TxBD[I].
The Ethernet controller then proceeds to the next TxBD in the table. In this way, the core
can be interrupted after each frame, after each buffer, or after a specific buffer is sent. If
TxBD[PAD] = 1, the Ethernet controller pads short frames to the value of the minimum
frame length register (MINFLR), described in Table 36-2.
To rearrange the transmit queue before the CP finishes sending all frames, issue a
command. This can be useful for transmitting expedited data
GRACEFUL STOP TRANSMIT
ahead of previously linked buffers or for error situations. When the
GRACEFUL STOP
command is issued, the Ethernet controller stops immediately if no transmission
TRANSMIT
is in progress or continues transmission until the current frame either finishes or terminates
with a collision. When the Ethernet controller is given the command,
RESTART TRANSMIT
it resumes transmission. The Ethernet controller sends bytes least-significant nibble first.
36.5 Ethernet Channel Frame Reception
The Ethernet receiver is designed to work with almost no core intervention and can perform
address recognition, CRC checking, short frame checking, maximum DMA transfer
checking, and maximum frame-length checking.
When the core enables the Ethernet receiver, it enters hunt mode when RX_DV is asserted
as long as COL remains negated (full-duplex mode ignores COL). In hunt mode, as data is
shifted into the receive shift register four bits at a time, the contents of the register are
compared to the contents of the SYN2 field in the FCC's data synchronization register
(FDSR). When the registers match, the hunt mode is terminated and character assembly
begins.
MOTOROLA Chapter 36. Fast Ethernet Controller 36-7
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