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Error
Transmitter
When this error occurs, the channel terminates buffer transmission, transmit an ABORT sequence
Underrun
(a sequence which will generate CRC error on the frame), closes the buffer, sets the underrun (U)
bit in the BD, and generates the TXE interrupt if it is enabled. The channel resumes transmission
after receiving the
CTS Lost during
When this error occurs, the channel terminates buffer transmission, closes the buffer, sets
Frame
TxBD[CT], and generates a TXE interrupt (if it is enabled). The channel resumes transmission after
Transmission
receiving the
Table 37-5 describes HDLC reception errors, which are reported through the RxBD.
Error
Overrun Error
The HDLC controller maintains an internal FIFO buffer for receiving data. The CP begins
programming the SDMA channel and updating the CRC whenever data is received in the FIFO
buffer. When a receive FIFO overrun occurs, the channel writes the received data byte to the internal
FIFO buffer over the previously received byte. The previous byte and the frame status are lost. The
channel closes the buffer with RxBD[OV] set and generates the RXF interrupt if it is enabled. The
receiver then enters hunt mode. Even if the overrun occurs during a frame whose address is not
matched in the address recognition logic, an RxBD with data length two is opened to report the
overrun and the RXF interrupt is generated if it is enabled.
CD Lost During
When this error occurs, the channel terminates frame reception, closes the buffer, sets RxBD[CD],
Frame Reception
and generates the RXF interrupt if it is enabled. This error has highest priority. The rest of the frame
is lost and other errors are not checked in that frame. At this point, the receiver enters hunt mode. If
CD is Lost during the first 8 serial bits it will not be reported as CD Lost error and there will be no
indication of error.
Abort Sequence The HDLC controller detects an abort sequence when seven or more consecutive ones are received.
When this error occurs and the HDLC controller receives a frame, the channel closes the buffer by
setting RxBD[AB] and generates the RXF interrupt (if enabled). The channel also increments the
abort sequence counter. The CRC and nonoctet error status conditions are not checked on aborted
frames. The receiver then enters hunt mode. When an abort sequence is received, the user is given
no indication that an HDLC controller is not currently receiving a frame.
Nonoctet Aligned
When this error occurs, the channel writes the received data to the data buffer, closes the buffer, sets
Frame
the Rx nonoctet aligned frame bit RxBD[NO], and generates the RXF interrupt (if it is enabled). The
CRC error status should be disregarded on nonoctet frames. After a nonoctet aligned frame is
received, the receiver enters hunt mode. An immediate back-to-back frame is still received. The
nonoctet data portion may be derived from the last byte in the buffer by finding the least-significant
set bit, which marks the end of valid data as follows:
CRC Error
When this error occurs, the channel writes the received CRC to the data buffer, closes the buffer,
sets RxBD[CR], and generates the RXF interrupt (if it is enabled). The channel also increments the
CRC error counter. After receiving a frame with a CRC error, the receiver enters hunt mode. An
immediate back-to-back frame is still received. CRC checking cannot be disabled, but the CRC error
can be ignored if checking is not required.
MOTOROLA
Freescale Semiconductor, Inc.
Table 37-4. HDLC Transmission Errors
command.
RESTART TRANSMIT
command.
RESTART TRANSMIT
Table 37-5. HDLC Reception Errors
msb
Valid data
Chapter 37. FCC HDLC Controller
For More Information On This Product,
Go to: www.freescale.com
Description
Description
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Programming Model
lsb
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37-7
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