Motorola PowerQUICC II MPC8280 Series Reference Manual page 1031

In the VC-level translation, the VCI is compressed with the VC_MASK to generate a
pointer to the VC-level table entry containing the received cell's channel code. The VC
table should reside in external memory.
Figure 31-5 shows an example of address compression.
4 bit
12 bit
PHY Addr VPI
0000
0000 00011111
VPpointer 0b00011
16 bit
VCI
00000111 11110000
VCpointer
15 bit
1 bit
—
MS
Ch Code[15–0]
0
Figure 31-5. Address Compression Mechanism
Figure 31-5 shows VP_MASK selecting five VPI bits to index the VP-level table. The
VP-level table entry contains the 16-bit mask (VC_MASK) and the VC-level table offset
(VCOFFSET) for the next level of address mapping. The VC_MASK selects VCI bits
4–10, which is used with VCT_BASE and VCOFFSET to indicate the received cell's
channel code. Address compression field descriptions are shown in Table 31-3.
Table 31-3. Field Descriptions for Address Compression
Field
PHY In multiple PHY mode, this field contains the 4 least-significant bits of the current channel's physical
Addr address. Because this comparison field is limited to 4 bits, two sets of look-up tables are needed if using
more than 16 PHYs.The msb of the PHY address (bit 4) selects between the two sets of tables. If the msb
is zero, the CP accesses the tables at VPT_BASE and VCT_BASE; if the msb is set, the CP uses
VPT1_BASE and VCT1_BASE. See Section 16.4.1, "CMX UTOPIA Address Register (CMXUAR)."
In single PHY mode, clear this field.
VCI, VPI The VCI and VPI of the current channel.
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
Freescale Semiconductor, Inc.
VP_MASK
VCT_BASE
16 bit
31
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VCI/VPI Address Lookup Mechanism
VP-level addressing table
(in dual-port RAM recommended)
0
VPT_BASE
32-bit entries
16 bit
VC_MASK
VC-level addressing tables
(in external memory)
32-bit entries
Description
31
16 bit
VCOFFSET
31-17