Motorola PowerQUICC II MPC8280 Series Reference Manual page 1210

AAL2 Exceptions
Table 33-15 describes the interrupt queue entry fields for the VC. All the receive error
events are enabled by setting RCT[EM].
Table 33-15. AAL2 Interrupt Queue Entry CID = 0 Field Descriptions
Offset Bits Name
0x00 0 V
1 —
2 W
3–10 CID
11 —
12-15 Error_Code A receive error was detected.
0x02 — CC
33-42
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Valid interrupt entry
0 This interrupt queue entry is free and can be used by the CP.
1 This interrupt queue entry is valid. The host should read this interrupt and clear this
bit.
—
Wrap bit. When set, this is the last interrupt circular table entry. During initialization,
the host must clear all W bits in the table except the last one, which must be set.
CID number. Equals zero. This exception applies to the whole cell.
Reserved
0000 Parity error of the OSF.
0001 The STF sequence number is incorrect.
0010 The number of octets expected to overlap into this cell does not match the OSF.
0011 OSF is greater than 47.
0100 A packet HEC error was detected.
0101 The length of the CPS packet exceeds the Max_SDU_Length.
0111 A packet HEC error was detected in a split header packet.
Channel code specifies the ATM channel number associated with this interrupt.
MPC8280 PowerQUICC II Family Reference Manual
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