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Motorola MPC750 User Manual
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
Audience
Organization
Suggested Reading
Conventions
Acronyms and Abbreviations
Terminology Conventions
Chapter 1
Overview
MPC750 Microprocessor Overview
MPC750 Microprocessor Features
Overview of the MPC750 Microprocessor Features
Instruction Flow
Instruction Queue and Dispatch Unit
Branch Processing Unit (BPU)
Completion Unit
Independent Execution Units
Integer Units (Ius)
Floating-Point Unit (FPU)
Load/Store Unit (LSU)
System Register Unit (SRU)
Memory Management Units (Mmus)
On-Chip Instruction and Data Caches
L2 Cache Implementation (Not Supported in the MPC740)
System Interfacelbus Interface Unit (BIU)
Signals
Signal Configuration
Clocking
MPC750 Microprocessor: Implementation
Powerpc Registers and Programming Model
Instruction Set
Powerpc Instruction Set
MPC750 Microprocessor Instruction Set
On-Chip Cache Implementation
Powerpc Cache Model
Exception Model
Powerpc Exception Model
MPC7S0 Microprocessor Exception Implementation
Memory Management
Powerpc Memory Management Model
MPC7S0 Microprocessor Memory Management Implementation
Instruction Timing
Power Management
Thermal Management
Performance Monitor
Chapter 2 MPC750 Processor Programming Model
The MPC7S0 Processor Register Set
Register Set
Instruction Address Breakpoint Register (IABR)
Hardware Implementation-Dependent Register 0
Hardware Implementation-Dependent Register 1
Performance Monitor Registers
Monitor Mode Control Register 0 (MMCRO)
User Monitor Mode Control Register 0 (UMMCRO)
Monitor Mode Control Register 1 (Mmcrl)
User Monitor Mode Control Register 1 (Ummcrl)
Performance Monitor Counter Registers (PMC I-PMC4)
User Performance Monitor Counter Registers (UPMCI-UPMC4)
Sampled Instruction Address Register (SIA)
User Sampled Instruction Address Register (USIA)
Sampled Data Address Register (SDA) and User Sampled Data Address Register (USDA)
Instruction Cache Throttling Control Register (ICTC)
Thermal Management Registers (THRMI-THRM3)
L2 Cache Control Register (L2CR)
Reset Settings
Operand Conventions
Floating-Point Execution Models-UISA
Data Organization in Memory and Data Transfers
Alignment and Misaligned Accesses
Floating-Point Operand
Instruction Set Summary
Classes of Instmctions
Definition of Boundedly Undefined
Defined Instmction Class
Illegal Instmction Class
Reserved Instmction Class
Addressing Modes
Memory Addressing
Memory Operands
Effective Address Calculation
Synchronization
Context Synchronization
Execution Synchronization
Instruction Set Overview
Powerpc UISA Instmctions
Integer Instmctions
Integer Arithmetic Instmctions
Integer Compare Instmctions
Integer Logical Instmctions
Integer Rotate and Shift Instmctions
Floating-Point Instmctions
Floating-Point Arithmetic Instmctions
Floating-Point Multiply-Add Instmctions
Floating-Point Rounding and Conversion Instmctions
Floating-Point Compare Instmctions
Floating-Point Status and Control Register Instmctions
Floating-Point Move Instmctions
Load and Store Instmctions
Self-Modifying Code
Integer Load and Store Address Generation
Register Indirect Integer Load Instmctions
Integer Store Instmctions
Integer Store Gathering
Integer Load and Store with Byte-Reverse Instmctions
Integer Load and Store Multiple Instmctions
Integer Load and Store String Instmctions
Floating-Point Load and Store Address Generation
Branch and Flow Control Instructions
Branch Instruction Address Calculation
Branch Instructions
Condition Register Logical Instructions
Trap Instructions
System Linkage Instruction-UISA
Processor Control Instructions-UISA
Move To/From Condition Register Instructions
Move To/From Special-Purpose Register Instructions (UISA)
Memory Synchronization Instructions-UISA
Powerpc VEA Instructions
Processor Control Instructions-VEA
Memory Synchronization Instructions-VEA
Memory Control Instructions-VEA
User-Level Cache Instructions-VEA
Optional External Control Instructions
Powerpc OEA Instructions
System Linkage Instructions-OEA
Processor Control Instructions-OEA
Memory Control Instructions-OEA
Supervisor-Level Cache Management Instruction-(OEA)
Segment Register Manipulation Instructions (OEA)
Translation Lookaside Buffer Management Instructions-(OEA)
Recommended Simplified Mnemonics
Chapter 3
L 1 Instruction and Data Cache Operation
Data Cache Organization
Instruction Cache Organization
Memory and Cache Coherency
Memory/Cache Access Attributes (WIMG Bits)
Mel Protocol
Mel Hardware Considerations
Coherency Precautions in Single Processor Systems
Coherency Precautions in Multiprocessor Systems
MPC750-Lnitiated Load/Store Operations
Performed Loads and Stores
Sequential Consistency of Memory Accesses
Atomic Memory References
Cache Control
Cache Control Parameters in HIDO
Data Cache Flash Invalidation
Data Cache Enabling/Disabling
Data Cache Locking
Instruction Cache Flash Invalidation
Instruction Cache Enabling/Disabling
Instruction Cache Locking
Cache Control Instructions
Data Cache Block Flush (Debt')
Instruction Cache Block Invalidate (Icbi)
Cache Operations
Cache Block Replacement/Castout Operations
Cache Flush Operations
Data Cache-Block-Fill Operations
Instruction Cache-Block-Fill Operations
Data Cache-Block-Push Operation
Enveloped High-Priority Cache-Block-Push Operation
Read Operations and the Mel Protocol
Bus Operations Caused by Cache Control Instructions
Snooping
Snoop Response to 60X Bus Transactions
Transfer Attributes
Bus Interface
Mel State Transactions
Chapter 4 MPC750 Microprocessor Exceptions
Exception Recognition and Priorities
Exception Processing
Enabling and Disabling Exceptions
Steps for Exception Processing
Setting MSR[RI]
Returning from an Exception Handler
Process Switching
Exception Definitions
System Reset Exception (Oxool00)
Machine Check Exception (Ox00200)
Machine Check Exception Enabled (MSR[ME] 1)
Checkstop State (MSR[ME] = 0)
Lsi Exception (Ox00400)
External Interrupt Exception (Ox00500)
Alignment Exception (Ox00600)
Program Exception (Ox00700)
Floating-Point Unavailable Exception (Ox00800)
Decrementer Exception (Ox00900)
System Call Exception (Oxoocoo)
Trace Exception (Oxoodoo)
Floating-Point Assist Exception (Oxooeoo)
Performance Monitor Interrupt (Oxoofoo)
Instruction Address Breakpoint Exception (Ox01300)
System Management Interrupt (Ox01400)
Thermal Management Interrupt Exception (Ox01700)
Chapter 5
Memory Management
MMU Overview
Memory Addressing
MMU Organization
Address Translation Mechanisms
Memory Protection Facilities
Page History Information
General Flow Ofmmu Address Translation
Real Addressing Mode and Block Address Translation Selection
Page Address Translation Selection
MMU Exceptions Summary
MMU Instructions and Register Summary
Real Addressing Mode
Block Address Translation
Memory Segment Model
Page History Recording
Referenced Bit
Changed Bit
Scenarios for Referenced and Changed Bit Recording
Page Memory Protection
TLB Description
TLB Organization
TLB Invalidation
Page Address Translation Summary
Page Table Search Operation
Page Table Updates
Segment Register Updates
Chapter 6
Instruction Timing
Terminology and Conventions
Instruction Timing Overview
Timing Considerations
General Instruction Flow
Instruction Fetch Timing
Cache Arbitration
Cache Hit
Cache Miss
L2 Cache Access Timing Considerations (MPC750 Only)
Instruction Dispatch and Completion Considerations
Rename Register Operation
Instruction Serialization
Execution Unit Timings
Branch Processing Unit Execution Timing
Branch Folding and Removal of Fall-Through Branch Instructions
Branch Instructions and Completion
Branch Prediction and Resolution
Static Branch Prediction
Predicted Branch Timing Examples
Integer Unit Execution Timing
Floating-Point Unit Execution Timing
Effect of Floating-Point Exceptions on Performance
Load/Store Unit Execution Timing
Effect of Operand Placement on Performance
Integer Store Gathering
System Register Unit Execution Timing
Memory Performance Considerations
Caching and Memory Coherency
Effect Oftlb Miss
Instruction Scheduling Guidelines
Branch, Dispatch, and Completion Unit Resource Requirements
Branch Resolution Resource Requirements
Dispatch Unit Resource Requirements
Completion Unit Resource Requirements
Instruction Latency Summary
Chapter 7
Signal Descriptions
Signal Configuration
Signal Descriptions
Address Bus Arbitration Signals
Bus Request (BR)-Output
Bus Grant (BG)-Input
Address Bus Busy (ABB)
Address Bus Busy (ABB)-Output
Address Bus Busy (ABB)-Input
Address Transfer Start Signals
Transfer Start (TS)
Transfer Start (TS)-Output
Transfer Start (TS)-Input
Address Transfer Signals
Address Bus (A[0-31])
Address Bus Parity (AP[0-3])
Address Transfer Attribute Signals
Transfer Type (TT[O-4])
Transfer Type (TT[O-4])-Output
Transfer Burst (TBST)
Transfer Burst (TBST)-Output
Transfer Burst (TBST)-Input
Cache Inhibit (CI)-Output
Write-Through (WT)-Output
Global (GBL)
Global (GBL)-Output
Global (GBL)-Input
Address Acknowledge (AACK)-Input
Address Retry (ARTRY)
Address Retry (ARTRY)-Output
Address Retry (ARTRY)-Input
Data Bus Arbitration Signals
Data Bus Grant (DBG)-Input
Data Bus Write Only (DBWO)-Input
Data Bus Busy (DBB)
Data Bus Busy (DBB)-Output
Data Bus Busy (DBB)-Input
Data Transfer Signals
Data Bus (DH[0-31], DL[0-31])
Data Bus Disable (DBDIS)-Input
Data Transfer Termination Signals
Transfer Acknowledge (TA)-Input
Transfer Error Acknowledge (TEA)-Input
System Status Signals
Interrupt (INT)-Input
System Management Interrupt (SMI)-Input
Machine Check Interrupt (MCP)-Input
Reset Signals
Hard Reset (HRESET)-Input
Soft Reset (SRESET)-Input
Processor Status Signals
Quiescent Request (QREQ)-Output
Quiescent Acknowledge (QACK)-Input
Reservation (RSRV)-Output
Time Base Enable (TBEN)-Input
TLBI Sync (TLBISYNC)-Input
L2 Cache Interface
L2 Address (L2ADDR[16-0])-Output
L2 Chip Enable (L2CE)-Output
L2 Write Enable (L2WE)-Output
L2 Low-Power Mode Enable (L2ZZ)-Output
IEEE 1149.1A-1993 Interface Description
Clock Signals
System Clock (SYSCLK)-Input
Clock out (CLK_OUT)-Output
Power and Ground Signals
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