Motorola PowerQUICC II MPC8280 Series Reference Manual page 931

28.4.10 SMC Transparent Event Register (SMCE)/Mask
Register (SMCM)
The SMC event register (SMCE) generates interrupts and reports events recognized by the
SMC channel. When an event is recognized, the SMC sets the corresponding SMCE bit.
Interrupts are masked in the SMCM, which has the same format as the SMCE. SMCE bits
are cleared by writing a 1 (writing 0 has no effect). Unmasked bits must be cleared before
the CP clears the internal interrupt request. The SMCE and SMCM registers are displayed
in Figure 28-14.
0
Field
Reset
R/W
Addr 0x11A86 (SMCE1), 0x11A96 (SMCE2)/ 0x11A8A (SMCM1), 0x11A9A (SMCM2)
Figure 28-14. SMC Transparent Event Register (SMCE)/Mask Register (SMCM)
Table 28-16 describes SMCE/SMCM fields.
Table 28-16. SMCE/SMCM Field Descriptions
Bits Name
0–2 — Reserved, should be cleared.
3 TXE Tx error. Set when an underrun error occurs on the transmitter channel. This event is not maskable
via the TxBD[I] bit.
4 — Reserved, should be cleared.
5 BSY Busy condition. Set when a character is received and discarded due to a lack of buffers. Reception
begins after a new buffer is provided. Executing an
wait for resynchronization.
6 TXB Tx buffer. Set after a buffer is sent. If the L bit of the TxBD is set, TXB is set when the last character
starts being sent. A one character-time delay is required to ensure that data is completely sent over
the transmit signal. If the L bit of the TxBD is cleared, TXB is set when the last character is written
to the transmit FIFO. A two character-time delay is required to ensure that data is completely sent.
7 RXB Rx buffer. Set when a buffer is received (after the last character is written) on the SMC channel and
its associated RxBD is now closed.
28.4.11 SMC Transparent NMSI Programming Example
The following example initializes the SMC1 transparent channel over its own set of signals.
The CLK9 signal supplies the transmit and receive clocks; the SMSYNx signal is used for
synchronization. (The SMC UART programming example uses a BRG configuration; see
Section 28.3.12, "SMC UART Controller Programming Example.")
1. Configure the port D pins to enable SMTXD1, SMRXD1, and SMSYN1. Set
PPARD[7,8,9] and PDIRD[9]. Clear PDIRD[7,8] and PSORD[7,8,9].
MOTOROLA
Freescale Semiconductor, Inc.
1 2
— TXE
Chapter 28. Serial Management Controllers (SMCs)
For More Information On This Product,
Go to: www.freescale.com
3 4 5
— BSY
0
R/W
Description
ENTER HUNT MODE
SMC in Transparent Mode
6 7
TXB RXB
command makes the receiver
28-31