Motorola PowerQUICC II MPC8280 Series Reference Manual page 1111

FIRSRx_HI, FIRSRx_LO, and by FTIRRx. Another feature of internal rate
expanded mode is an indication of transmit underrun error status per PHY. When
using internal rate expanded mode, the user assigns one of the baud-rate generators
(BRGs) to clock the four internal rate timers, and any timer can trigger any PHY.
31.15.1 FCC Transmit Internal Rate Mode
In internal rate mode the total transmission rate is the sum of the rates assigned for all
PHYs. This register controls how internal rate is configured. In internal rate mode
(GFEMR[TIREM] = 0), the internal rate assigned per PHY is configured by registers
FTIRR[0-3]. In internal rate expanded mode (GFEMR[TIREM] = 1), registers FTIRR[0-3]
control the available rates, but the PHY settings are configured in registers FIRPER,
FIRSR_HI and FIRSR_LO. In TIREM = 0 mode internal rate can only be used for
PHYs[0-3], whereas in TIREM = 1 mode up to 31 PHYs are supported. If TIREM = 1 mode
is selected, the transmit internal rate underrun (TIRU) status per PHY may be read at any
time in register FIRER.
31.15.1.1 FCC Transmit Internal Rate Register (FTIRRx)
The source clock of the internal rate timers is the BRGs clock,
which is configured in CMXUAR (refer to Section 16.4.1,
"CMX UTOPIA Address Register (CMXUAR)"). The
frequency of this clock must be less than one half of the FCC
Tx Clock of the UTOPIA interface.
If GFEMR[TIREM] = 0, the first four PHY devices (address 00– 03) on FCC1 and FCC2
have their own transmit internal rate registers (FTIRRx_PHY0–FTIRRx_PHY3) for use in
transmit internal rate mode. In this mode, the total transmission rate is determined by FCC
internal rate timers. As a master, the controller only polls the PHY's Clav status at the rate
determined by the internal rate. As a slave, the controller attempts to insert cells into the
FIFO at the internal rate. The controller can handle a lag of up to seven cells per PHY
between the programmable and actual bus rate. When the cell count mismatch reaches
seven, TIRU event is reported, see Section 31.13.3, "ATM Event Register (FCCE)/Mask
Register (FCCM)". Note that a mismatch occurs if the PHY rate or the CPM performance
are lower then the internal rate.
If GFEMR[TIREM] = 1, FTIRRx are used as group timers and PHYs at addresses 0-30 are
assigned to a rate group by FIRSRx_HI and FIRSRx_LO.
FTIRRx, shown in Figure 31-62, includes the initial value of the internal rate timer. The
source clock of the internal rate timers is supplied by one of four baud-rate generators
selected in CMXUAR; see Section 16.4.1, "CMX UTOPIA Address Register
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
Freescale Semiconductor, Inc.
Transmission Rate Modes—External, Internal, and Expanded Internal
NOTE
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