Motorola PowerQUICC II MPC8280 Series Reference Manual page 1456

causes, 5-1
external HRESET flow, 5-3
external SRESET flow, 5-3
power-on reset flow, 5-2
receiver reset sequence, SCC, 20-27
resetting registers and parameters for all channels,
14-13
software watchdog reset, 5-1
transmitter reset sequence, SCC, 20-26
RFCR (Rx buffer function code register)
overview, 20-15
RISC microcontroller, seeCommunications processor
(CP)
RISC timer tables
CP loading tracking, 14-30
features list, 14-25
initializing RISC timer tables, 14-28
interrupt handling, 14-29
overview, 14-25
parameter RAM, 14-25
RAM usage, 14-26
RTMR, 14-27
scan algorithm, 14-29
SET TIMER command, 14-28
table entries, 14-27
timer counts, comparing, 14-30
TM_CMD, 14-27
tracking CP loading, 14-30
RMR (reset mode) register, 5-5
RSR (reset status) register, 5-4
RSTATE (internal receiver state) register, 29-10
RTMR (RISC timer mask register), 14-27
RTSCR (RISC time-stamp control register), 14-10
RTSR (RISC time-stamp register), 14-11
S
SCC memory map, 3-18
SCCE (SCC event) register
BISYNC mode, 23-15
HDLC mode, 22-13
transparent mode, 24-12
UART mode, 21-20
SCCE register
Ethernet mode, 25-21
SCCM (SCC mask) register
BISYNC mode, 23-15
HDLC mode, 22-13
transparent mode, 24-12
UART mode, 21-20
SCCM register
Ethernet mode, 25-21
SCCS (SCC status) register
BISYNC mode, 23-16
Index-22
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HDLC mode, 22-15
transparent mode, 24-13
UART mode, 21-22
SCIT programming, 15-34
SCPRR_H (CPM high interrupt priority register), 4-20
SCPRR_L (CPM low interrupt priority register), 4-21
SDMA channels
bus arbitration, 19-2
bus transfers, 19-2
LDTEA, 19-4
LDTEM, 19-4
overview, 19-1
PDTEA, 19-4
PDTEM, 19-4
programming model, 19-3
registers, 19-3
SDMR, 19-4
SDSR, 19-3
SDMR (SDMA mask register), 19-4
SDRAM interface, see SDRAM machine
SDSR (SDMA status register), 19-3
Serial communications controllers (SCCs)
AppleTalk mode
connecting to AppleTalk, 26-3
operating LocalTalk frame, 26-1
overview, 26-1
programming example, 22-25, 26-5
programming the controller, 26-3
BISYNC mode
commands, 23-5
control character recognition, 23-6
error handling, 23-9
frame reception, 23-3
frame transmission, 23-2
overview, 23-1
parameter RAM, 23-3
programming example, 23-18
programming the controller, 23-17
receiving synchronization sequence, 23-9
RxBD, 23-12
sending synchronization sequence, 23-9
TxBD, 23-14
Ethernet mode
address recognition, 25-12
collision handling, 25-14
commands, 25-10
connecting to Ethernet, 25-4
error handling, 25-14
frame reception, 25-6
hash table algorithm, 25-13
loopback, 25-14
overview, 25-1
programming example, 25-23
programming the controller, 25-10
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