Motorola PowerQUICC II MPC8280 Series Reference Manual page 1459

transparent mode, 28-31
UART mode, 28-20
SMCM (SMC mask) register
GCI mode, 28-37
transparent mode, 28-31
UART mode, 28-20
SMCMRs (SMC mode registers), 28-3
SPCOM, 27-20
SPCOM (SPI command) register, 39-11
SPI
clocking and pin functions, 27-3
master mode, 27-5, 27-9
parameter RAM memory map, 27-13
programming model, 27-17
slave, 27-3
SPI block diagram, 27-5, 27-9
SPISEL, 27-26, 27-27
SPI block diagram, 27-5, 27-9
SPI buffer descriptor ring, 27-23
SPI memory map, 3-22
SPI receive buffer descriptor, 27-26
SPIE, 27-21
SPIE (SPI event) register, 39-10
SPIM (SPI mask) register, 39-10
SPMODE (SPI mode) register, 39-7
SWR (software watchdog register), 4-8
SWSR (software service register), 4-39
SYPCR (system protection control register), 4-38
System integration timers memory map, 3-4
System interface unit (SIU)
60x bus monitor function, 4-3
BCR, 4-27
block diagram, 4-2
bus monitor, 4-4
clocks, 4-4
configuration functions, 4-2
configuration/protection logic block diagram, 4-3
encoding the interrupt vector, 4-15
FCC relative priority, 4-13
highest priority interrupt, 4-14
IMMR, 4-37
interrupt controller features list, 4-8
interrupt source priorities, 4-11
interrupt vector calculation, 4-15
interrupt vector encoding, 4-15
interrupt vector generation, 4-15
L_TESCR1, 4-43
L_TESCR2, 4-44
LCL_ACR, 4-32
LCL_ALRH, 4-33
LCL_ALRL, 4-34
local bus monitor function, 4-3
masking interrupt sources, 4-14
MCC relative priority, 4-13
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Freescale Semiconductor, Inc.
Index
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periodic interrupt timer (PIT), 4-5
periodic interrupt timer (PIT) function, 4-3
pin multiplexing, 4-51
PISCR, 4-47
PITC, 4-48
PITR, 4-49
port C interrupts, 4-17
PPC_ACR, 4-30
PPC_ALRH, 4-31
PPC_ALRL, 4-32
programming model, 4-18
registers, 4-18
SCC relative priority, 4-13
SCPRR_H, 4-20
SCPRR_L, 4-21
SICR, 4-18
SIEXR, 4-26
signal multiplexing, 4-51
SIMR_H, 4-23, 4-24
SIPNR_H, 4-22
SIPNR_L, 4-23
SIPRR, 4-19
SIUMCR, 4-34
SIVEC, 4-25
software watchdog timer, 4-6
SWR, 4-8
SWSR, 4-39
SYPCR, 4-38
system protection, 4-2
TESCR1, 4-40
TESCR2, 4-42
time counter (TMCNT)
function, 4-3
overview, 4-5
timers, 4-4
TMCNT, 4-45
TMCNTAL, 4-46
TMCNTSC, 4-45
system interface unit,, 19-2
System register unit (SRU), 2-8
T
TBST (transfer burst) signal, 8-13
TC layer
block diagram, 35-4
cell counters, 35-13
corrected, TC_CCCx, 35-13
errored, TC_ECCx, 35-13
filtered, TC_FCCx, 35-13
IDLE, TC_ICCx, 35-13
received, TC_RCCx, 35-13
transmitted, TC_TCCx, 35-13
features, 35-2
Index-25