Motorola PowerQUICC II MPC8280 Series Reference Manual page 1437

exceptions, 31-85
external rate mode, 31-7
FCCE, 31-94
FCCM, 31-94
features list, 31-2
FPSMR, 31-91
GFMR register, 31-91
global mode entry (GMODE), 31-43
internal rate mode, 31-7
interrupt queues, 31-85
maximum performance configuration, 31-104
OAM performance monitoring, 31-31, 31-65
OAM support, 31-29
operations and maintenance (OAM) support, 31-29
overview, 31-5
parameter RAM, 31-40
performance monitoring, 31-9
performance, maximum (configuration), 31-104
programming model, 31-91
receive connection table (RCT)
AALn protocol-specific RCTs, 31-50, 31-50-??,
31-53
ATM channel code, 31-45
overview, 31-44
raw cell queue, 31-20
RCT entry format, 31-47
registers, 31-91
RxBD, 31-74
RxBD extension, 31-79
SRTS generation using external logic, 31-103
transmit connection table (TCT)
AALn protocol-specific TCTs, 31-58
ATM channel code, 31-45
overview, 31-44
TCT entry format, 31-54
transmit connection table extension (TCTE)
ABR protocol-specific, 31-62
ATM channel code, 31-45
overview, 31-44
UBR+ protocol-specific, 31-62
VBR protocol-specific, 31-61
transmit rate modes, 31-7
TxBD, 31-79
TxBD extension, 31-83
UDC extended address mode, 31-35
UEAD_OFFSET determination, 31-42
UNI statistics table, 31-84
user-defined cells (UDC)
extended address mode, 31-35
overview, 31-35
RxBD extension (AAL5/AAL1), 31-79
TxBD extension (AAL5/AAL1), 31-83
user-defined RxBD extension (AAL5/AAL1),
31-79
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Index
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user-defined TxBD extension (AAL5/AAL1), 31-83
UTOPIA interface, 31-87
VCI filtering, 31-43
VCI/VPI address lookup, 31-15
VC-level address compression tables (VCLT),
31-19
VP-level address compression table (VPLT), 31-18
B
Baud-rate generator (BRG)
BRGCLK, 40-2
memory map, 3-17
BCR (bus configuration register), 4-27
BDLE (SCC BISYNC DLE) register, 23-8
BISYNC mode
commands, 23-5
control character recognition, 23-6
error handling, 23-9
frame reception, 23-3
frame transmission, 23-2
overview, 23-1
parameter RAM, 23-3
programming example, 23-18
programming the controller, 23-17
receiving synchronization sequence, 23-9
RxBD, 23-12
sending synchronization sequence, 23-9
TxBD, 23-14
block diagram
dual-port RAM, 14-18
system PLL,, 10-6
Block diagrams
cascaded mode, 18-4
communications processor (CP), 14-6
communications processor module (CPM), 14-3
CPM multiplexing logic (CMX), 16-2
DPLL receiver, 20-22
dual-bus architecture, 11-3
Fast Ethernet, 36-3
FCC overview, 30-3
2
I C controller, 40-1
IEEE 1149.1 test access port, 13-2
parallel I/O ports, 41-6
SCC block diagram, 20-2
serial interface, 15-2
serial peripheral interface (SPI), 39-1
system interface unit (SIU)
periodic interrupt timer, 4-6
SIU block diagram, 4-2
software watchdog timer, 4-7
system configuration/protection logic, 4-3
time counter (TMCNT), 4-5
timers, 18-1
Index-3