Motorola PowerQUICC II MPC8280 Series Reference Manual page 752

Handling Errors in the SCC UART Controller
.
0 1 2
Field — FSB
Reset 0 1111
R/W
Addr
Figure 21-5. Asynchronous UART Transmitter
Table 21-6 describes DSR fields.
Bit Name
0 — 0b0
1–4 FSB Fractional stop bits. For 16× oversampling:
1111 Last transmitted stop bit 16/16. Default value after reset.
1110 Last transmitted stop bit 15/16.
...
1000 Last transmitted stop bit 9/16.
0xxx Invalid. Do not use.
For 32× oversampling:
1111 Last transmitted stop bit 32/32. Default value after reset.
1110 Last transmitted stop bit 31/32.
...
0000 Last transmitted stop bit 17/32.
For 8× oversampling:
1111 Last transmitted stop bit 8/8. Default value after reset.
1110 Last transmitted stop bit 7/8.
1101 Last transmitted stop bit 6/8.
1100 Last transmitted stop bit 5/8.
10xx Invalid. Do not use.
0xxx Invalid. Do not use.
The UART receiver can always receive fractional stop bits. The next character's start bit can begin
any time after the three middle samples have been taken.
5–6 — 0b11
7–8 — 0b00
9–14 — 0b111111
15 — 0b0
21.15 Handling Errors in the SCC UART Controller
The UART controller reports character reception and transmission error conditions via the
BDs, the error counters, and the SCCE. Modem interface lines can be monitored by the port
C pins. Transmission errors are described in Table 21-7.
21-12
Freescale Semiconductor, Inc.
3 4 5 6
— —
1 1
Table 21-6. DSR Fields Descriptions
MPC8280 PowerQUICC II Family Reference Manual
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7 8 9 10 11
— — — — —
0 0 1 1 1
R/W
Description
12 13 14 15
— — — —
1 1 1 0
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