Motorola PowerQUICC II MPC8280 Series Reference Manual page 472

SDRAM Machine
Table 11-17 describes MPTPR fields.
Bits Name
0–7 PTP Refresh timers prescaler. Determines the period of the memory refresh timers input clock. It divides
the bus clock. Prescaler clock frequency = Bus frequency / (PTP + 1).
8–15 — Reserved, should be cleared
11.3.13 60x Bus Error Status and Control Registers (TESCRx)
These registers indicate the source of an error that caused TEA or MCP to be asserted on
the 60x bus. See Section 4.3.2.10, "60x Bus Transfer Error Status and Control Register 1
(TESCR1)," and Section 4.3.2.11, "60x Bus Transfer Error Status and Control Register 2
(TESCR2)."
11.3.14 Local Bus Error Status and Control Registers
(L_TESCRx)
These registers indicate the source of an error that causes TEA or MCP to be asserted on
the local bus. See Section 4.3.2.12, "Local Bus Transfer Error Status and Control Register 1
(L_TESCR1)," and Section 4.3.2.13, "Local Bus Transfer Error Status and Control
Register 2 (L_TESCR2)."
11.4 SDRAM Machine
The MPC8280 provides one SDRAM interface (machine) for the 60x bus and one for the
local bus. The machines provide the necessary control functions and signals for
JEDEC-compliant SDRAM devices.
Each bank can control a SDRAM device on the 60x or the local bus. Table 11-18 describes
the SDRAM interface signals controlled by the memory controller.
60x Bus
PSDRAS
SDCAS
DQM[0–7]
11-34
Freescale Semiconductor, Inc.
Table 11-17. MPTPR Field Descriptions
Table 11-18. SDRAM Interface Signals
Local Bus
CS[0–11]
LSDRAS
LSDCAS
SDWE LSDWE
SDA10 LSDA10
LDQM[0–3]
MPC8280 PowerQUICC II Family Reference Manual
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Description
Comments
Device select
RAS
CAS
WEN
"A10" control
Byte select
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