Motorola PowerQUICC II MPC8280 Series Reference Manual page 1171

UTOPIA
PHY4
33.2 Features
The MPC8280's AAL2 features are as follows:
• Fully complies with ITU-T I.363.2 (09/97 and 11/00) and ITU-T I.366.1 (06/98)
specifications.
• Number of AAL2 external channels supported is subject to internal memory
constraints
— Each external channel requires space for one Transmit Queue Descriptor in
internal memory. Typically, up to 1000 external channels can be supported.
• Supports CBR, VBR and UBR+ traffic types
— PCR pacing (with optional Timer_CU)
— VBR pacing (with optional Timer_CU)
— UBR+ pacing (no Timer_CU support)
• Priority mechanism for transmitting per VC. The priority mechanism provides for
TX queues having equal or differing priorities. The SSSAR TX queues can be
prioritized flexibly among the CPS TX queues.
• Timer_CU support
• NoSTF mode support
• Support for partially filled cells
• User-defined cells (as described in Section 31.7, "User-Defined Cells (UDC)").
• Interrupt indications include the ATM channel number, the CID, and the event type.
The events reported are TX buffer not ready, TX buffer transmitted, RX buffer not
ready, RX buffer, RX SSSAR frame, and RX AAL2 error events.
• CPS switching
— Switching from a receive PHY
transmit PHY
— Partial packet discard support
MOTOROLA
Freescale Semiconductor, Inc.
VP=5|VC=20|CID=13
X
Figure 33-3. AAL2 Switching Example
| VP
1
| VP | VC | CID
2 2 2 2
Chapter 33. ATM AAL2
For More Information On This Product,
Go to: www.freescale.com
VP=27|VC=3|CID=212
| VC | CID combination to another
1 1 1
combination
Features
UTOPIA
PHY7
33-3