Motorola PowerQUICC II MPC8280 Series Reference Manual page 1339

Freescale Semiconductor, Inc.
HDLC Channel Frame Reception Processing
set (working in multibuffer mode), only the R bit is cleared. In either mode, an interrupt can
be issued if the I bit in the TxBD is set. The HDLC controller then proceeds to the next
TxBD in the table. In this way, the core can be interrupted after each buffer, after a specific
buffer, after each frame, or after a number of frames.
To rearrange the transmit queue before the CP has sent all buffers, issue the
STOP TRANSMIT
command. This can be useful for sending expedited data before previously linked buffers
or for error situations. When receiving the command, the HDLC controller
STOP TRANSMIT
aborts the current frame transmission and starts transmitting idles or flags. When the HDLC
controller is given the command, it resumes transmission. To insert a
RESTART TRANSMIT
high-priority frame without aborting the current frame, the
GRACEFUL STOP TRANSMIT
command can be issued. A special interrupt (GRA) can be generated in the event register
when the current frame is complete.
37.3 HDLC Channel Frame Reception Processing
The HDLC receiver is designed to work with almost no core intervention and can perform
address recognition, CRC checking, and maximum frame length checking. The received
frame is available for any HDLC-based protocol. When the core enables a receiver, the
receiver waits for an opening flag character. When it detects the first byte of the frame, the
HDLC controller compares the frame address against the user-programmable addresses.
The user has four 16-bit address registers and an address mask available for address
matching. The HDLC controller compares the received address field to the user-defined
values after masking with the address mask. The HDLC controller can also detect broadcast
(all ones) address frames if one address register is written with all ones.
If a match is detected, the HDLC controller checks the prefetched BD; if it is empty, it starts
transferring the incoming frame to the BD's associated buffer. When the buffer is full, the
HDLC controller clears BD[E] and generates an interrupt if BD[I] = 1. If the incoming
frame is larger than the buffer, the HDLC controller fetches the next BD in the table and, if
it is empty, continues transferring the frame to the associated buffer.
During this process, the HDLC controller checks for frames that are too long. When the
frame ends, the CRC field is checked against the recalculated value and written to the
buffer. The data length written to the last BD in the HDLC frame is the length of the entire
frame. This enables HDLC protocols that lose frames to correctly recognize a
frame-too-long condition.
The HDLC controller then sets the last buffer in frame bit, writes the frame status bits into
the BD, and clears the E bit and fetches the next BD. The HDLC controller then generates
a maskable interrupt, indicating that a frame was received and is in memory. The HDLC
controller then waits for a new frame. Back-to-back frames can be received separated only
by a single shared flag.
MOTOROLA Chapter 37. FCC HDLC Controller 37-3
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