Motorola PowerQUICC II MPC8280 Series Reference Manual page 1446

transfers, 19-6
IDMA parameter RAM,, 19-18
IDMR (IDMA mask registers), 19-25
IDSR (IDMA event (status) register), 19-25
IEEE 1149.1 test access port
block diagram, 13-2
boundary scan register, 13-3
instruction decoding, 13-6
instruction register, 13-5
nonscan chain operation, 13-7
overview, 13-1
restrictions, 13-7
TAP controller, 13-2
IMA, 34-1
FCC programming
registers, 34-24
features, 34-1
ATM features not supported, 34-4
impact on MPC8280 features, 34-4
MPC8280 versions supported, 34-3
PHY-layer devices supported, 34-4
references, 34-3
versions supported, 34-3
microcode architecture, 34-10
function partitioning, 34-10
plane management functions, 34-11
receive, 34-17
cell processing activation function, 34-20
cell processing task, 34-22
cell reception task, 34-18
IDCR-regulated cell processing, 34-21
on-demand cell processing, 34-20
summary, 34-19
transmit, 34-11
non-TRL operation, 34-14
transmit queue (ITC mode), 34-14
TRL operation, 34-12
user plan functions, 34-11
programming model, 34-23
APC programming, 34-54
ABR, 34-55
CBR, UBR, VBR, and UBR+, 34-55
data structure organization, 34-23
exceptions, 34-47
ICP cell reception exceptions, 34-49
interrupt queue entry, 34-48
FCC programming
IMA-specific parameters, 34-25
parameters, 34-24
GMODE, 34-24
RCELL_TMP_BASE, 34-24
TCELL_TMP_BASE, 34-24
group tables, 34-27
group receive control (IGRCNTL), 34-36
Index-12
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group receive state (IGRSTATE), 34-37
group receive table entry, 34-34
group transmit state (IGTSTATE), 34-30
ICP cell templates, 34-31
receive group frame size, 34-37
receive group order tables, 34-38
transmit group order table, 34-30
transmit table entry, 34-28
group transmit control (IGTCNTL),
34-29
IDCR timer programming, 34-50
FCC parameter shadow, 34-50
on-the-fly FCC parameter changes,
34-52
programming, 34-51
unavailable
34-50
IDCR counter algorithm, 34-53
IDCR events, 34-53
IDCR root parameters, 34-52
IDCR table entry, 34-52
IDCR_Init command, 34-52
master clock, 34-50
IMA FCC programming, 34-24
link tables, 34-39
link receive statistics table, 34-45
link receive table entry, 34-42
link receive control (ILRCNTL),
34-44
link receive state (ILRSTATE),
34-44
link transmit table entry, 34-39
ILTCNTL, 34-40
link transmit state (ILTSTATE),
34-41
transmit interrupt status (ITINT-
STAT), 34-41
root table, 34-25
control (IMACNTL), 34-27
structures in external memory, 34-46
transmit queues, 34-46
delay compression buffers (DCB),
34-47
protocol overview, 34-4
IMA cells, 34-7
control cells, 34-7
filler cells, 34-10
IMA frame overview, 34-5
introduction, 34-4
root table data structures, 34-23
software interface and requirements, 34-56
initialization procedure, 34-57
software model, 34-56
software procedures, 34-60
MPC8280 features,
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