Motorola PowerQUICC II MPC8280 Series Reference Manual page 1350

HDLC Event Register (FCCE)/Mask Register (FCCM)
• Tx data buffer pointer. The transmit buffer pointer, which contains the address of the
associated data buffer, can be even or odd. The buffer can reside in internal or
external memory. This value is never modified by the CP.
37.9 HDLC Event Register (FCCE)/Mask Register
(FCCM)
The FCCE is used as the HDLC event register when the FCC operates as an HDLC
controller. The FCCE reports events recognized by the HDLC channel and generates
interrupts. On recognition of an event, the HDLC controller sets the corresponding FCCE
bit. FCCE bits are cleared by writing ones; writing zeros does not affect bit values. All
unmasked bits must be cleared before the CP clears the internal interrupt request.
Interrupts generated by the FCCE can be masked in the HDLC mask register (FCCM),
which has the same bit format as FCCE. If an FCCM bit = 1, the corresponding interrupt
in the event register is enabled. If the bit is 0, the interrupt is masked.
Figure 37-7 represents the FCC/FCCM.
0 1 2
Field
Reset
R/W
Addr
16 17 18
Field
Reset
R/W
Addr
Figure 37-7. HDLC Event Register (FCCE)/Mask Register (FCCM)
Table 37-9 describes FCCE/FCCM fields.
37-14
Freescale Semiconductor, Inc.
3 4 5 6
—
0000_0000_0000_0000
0x11310 (FCCE1), 0x11330 (FCCE2), 0x11350 (FCCE3)/
0x11314 (FCCM1), 0x11334 (FCCM2), 0x11354 (FCCM3)
19 20 21 22
— FLG
0000_0000_0000_0000
0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/
0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3)
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7 8 9 10
GRA — TXE
R/W
23 24 25 26
IDL
R/W
11 12 13 14 15
RXF BSY TXB RXB
27 28 29 30 31
—
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