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Motorola DragonBall MC68328 User Manual

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MC68328 (DragonBall)
Integrated Processor
User's Manual
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
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MOTOROLA, 1995

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  Summary of Contents for Motorola DragonBall MC68328

  • Page 1 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
  • Page 2 Documentation Comments FAX 512-891-8593—Documentation Comments Only The Motorola High-Performance Embedded Systems Technical Communications Depart- ment provides a fax number for you to submit any questions or comments about this docu- ment or how to order other documents. We welcome your suggestions for improving our documentation.
  • Page 3 CHINA , Beijing 86 505-2180 HYBRID COMPONENTS RESELLERS FINLAND , Helsinki 358-0-35161191 Elmo Semiconductor (818) 768-7400 Car Phone 358(49)211501 Minco Technology Labs Inc. (512) 834-2022 FRANCE , Paris/Vanves 33(1)40 955 900 Semi Dice Inc. (310) 594-4631 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 4 PREFACE The MC68328 Integrated Portable System Processor User's Manual describes the program- ming, capabilities, and operation of the M68328; the MC68000 Family Programmer’s Refer- ence Manual provides instruction details for the EC000 core; and the Integrated Portable System Process: DragonBall Product Brief provides an overview of the M68328.
  • Page 5 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 6: Table Of Contents

    1.2.7 SIM28 Programming Model ..............1-10 Section 2 System Integration Module Module Operation ..................2-1 2.1.1 MC68328 Processor System Configuration..........2-1 2.1.1.1 System Control Register Functions ............2-1 2.1.1.2 System Protection Functions ..............2-2 2.1.2 Chip-Select and Wait-State Logic.............. 2-2 2.1.2.1...
  • Page 7 4.1.3 Line Buffer ....................4-2 4.1.4 Cursor Control Logic.................. 4-2 4.1.5 Frame Rate Control (FRC) ................ 4-2 4.1.6 LCD Interface .................... 4-3 Interfacing LCDC with LCD Panel ............... 4-3 Panel I/F Timing................... 4-4 viii MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 8 Gray Palette Mapping Register (GPMR) ..........4-19 Bandwidth Calculation and Saving ............4-20 4.8.1 Bus Overhead Considerations..............4-20 Section 5 Real-Time Clock Module Operating Characteristics ................5-1 5.1.1 Prescaler and Counter................5-1 5.1.2 Alarm ......................5-1 MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 9 Port C ......................7-5 7.1.5 Port D ......................7-6 7.1.6 Port E......................7-8 7.1.7 Port F......................7-9 7.1.8 Port G ...................... 7-10 7.1.9 Port J ....................... 7-11 7.1.10 Port K....................... 7-12 7.1.11 Port M ...................... 7-14 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 10 SPIM Data Register ................. 10-5 Section 11 Pulse-Width Modulator 11.1 Overview ....................11-1 11.2 Programmer’s Model.................. 11-2 11.2.1 PWM Control Register ................11-2 11.2.2 Period Register ..................11-4 11.2.3 Width Register ..................11-4 11.2.4 Counter ....................11-4 MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 11 Table of Contents Section 12 Pin Assignment Section 13 Electrical Characteristics 13.1 Maximum Ratings ..................13-1 13.2 Power Consumption .................. 13-1 13.3 AC Electrical Specification Definitions ............13-1 13.4 AC Electrical Specifications—Read and Write Cycles....... 13-1 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 12: Mc68328 Processor Overview

    1.1 KEY FEATURES The primary features of the MC68328 processor, illustrated in Figure 1, are as follows: • MC68EC000 Static Core Processor • 100% Compatibility with MC68000 And MC68EC000 Processors —24-Bit External and 32-Bit Internal Address Bus...
  • Page 13 CONTROL INFRA-RED MODULE SUPPORT PARALLEL I/O PORTS Figure 1. MC68328 Block Diagram • UART —Supports IrDA-Compliant Physical-Layer Protocol —8-Byte FIFOs for Rx and Tx • Two Separate Serial Peripheral Interface Ports (Master and Slave) —Support For External POCSAG Decoder (Slave) —Support for Digitizer For A/D Input or EEPROM (Master)
  • Page 14: Organization

    • LCD Control Module —Software Programmable Screen Size to Support Single (Non-Split) Monochrome/ STN Panels —Direct Drive Capability of Common LCD Drivers/Modules from Motorola and Other LCD Drive Manufacturers —Support as Many as 4 Grey Levels —Use System Memory as Display Memory •...
  • Page 15: Mc68328 Architecture

    1.2 MC68328 ARCHITECTURE To improve total system throughput and reduce component count, board size, and cost of system implementation, the MC68328 processor integrates a powerful MC68EC000 proces- sor, intelligent peripheral modules, and typical system interface logic. These functions include the system integration module (SIM28), timers, LCD controller, and more.
  • Page 16 In addition, operations on other data types such as memory addresses, status word data, etc. are provided in the instruction set. The 14 address modes listed in Table 1-1 include six basic types: 1. Register direct 2. Register indirect 3. Absolute 4. Program counter relative MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 17: Instruction Set Overview

    (through traps). 1.2.2 SYSTEM INTEGRATION MODULE The MC68328 SIM28 consists of several functions that control the system startup, initializa- tion, configuration, and the external bus with a minimum of external devices. The memory MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 18 1.0 memory cards. With the assistance of chip-select logic, wait states can be programma- ble. The hardware and software watchdog timers help users perform system protections. The interrupt controller accepts and resolves the priority from internal modules and exter- MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 19: System Configuration

    (PLL). The other option is for an external clock to directly drive the clock signal at the operational frequency. 1.2.2.3 CHIP-SELECT LOGIC. The MC68328 processor provides 16 programmable, gen- eral-purpose, chip-select signals. For a given chip-select block, users may choose: (1)
  • Page 20: Parallel General-Purpose I/O Ports

    1.2.5 Real-Time Clock A 32.76kHz or 38.4kHz crystal (the same as the clock synthesizer clock source) drives the real-time clock in the MC68328 processor and provides an alarm interrupt. 1.2.6 JTAG Test Access Port To assist in system diagnostics, the MC68328 processor includes dedicated user-accessi- ble test logic that is fully compliant with the IEEE 1149.1 standard for boundary-scan test-...
  • Page 21: Sim28 Programming Model

    Overview 1.2.7 SIM28 Programming Model The SIM28 programming model is listed in Table 1-3. 1-10 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 22 Port C Select Register Base+$418 PDDIR Port D Direction Register Base+$419 PDDATA Port D Data Register Base+$41A PDPUEN Port D Pullup Enable Register Base+$41C PDPOL Port D Polarity Register Base+$41D PDIRQEN Port D IRQ Enable Register MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 1-11...
  • Page 23: Period Register

    SPIM SPIM Data Register $0000 Base+$802 SPIMCONT SPIM SPIM Control/Status Register $0000 Base+$900 USTCNT UART UART Status/Control Register $0000 Base+$902 UBAUD UART UART Baud Control Register $003F Base+$904 UART UART RX Register $0000 1-12 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 24 SCR, then the base is $FFFFF000. Do not access any space within the 4K register space that is not defined in the above table. Unpredictable results may occur. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 1-13...
  • Page 25 Overview 1-14 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 26: System Integration Module

    MC68328 processor for their target systems. 2.1.1 MC68328 Processor System Configuration The MC68328 processor system configuration logic consists of a system control register (SCR) that lets users configure operation of the following functions: • Access permission of internal peripheral registers •...
  • Page 27: System Protection Functions

    To operate the software watchdog timer, refer to the timer section. 2.1.2 Chip-Select and Wait-State Logic The MC68328 processor provides a set of 16 general-purpose, programmable, chip-select signals arranged as 4 groups of 4 that includes two special-purpose chip-select signals.
  • Page 28: Programmable Data-Bus Size

    (1) use a chip-select configured as 16- bit data-bus width, and (2) connect to D7-D0. This balances more evenly the load on the two halves of the data bus in an 8-bit system. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 29 BBUSW pin during reset logic 0 or 1 for 8-bit and 16-bit wide data bus, respectively. The other chip-selects are initialized to be nonvalid, and so will not assert until they are pro- grammed and the valid bits set. MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 30: Overlap In Chip-Select Ranges

    2.5 Chip-Select Registers . 2.2 PROGRAMMING MODEL The various modules in the MC68328 processor, including the SIM28, contain registers that control the modules and provide status information from the modules. All of these registers reside in the top 4096-byte range ($FFFFF000 to $FFFFFFFF) of addresses in the memory map of the MC68EC000 core processor.
  • Page 31: Interrupt Controller Block

    2.3.1 Interrupt Controller Overview The interrupt-controller block supports 23 interrupts. Both edge- and level-sensitive inter- rupts are supported. A programmable vector can be generated for each interrupt level. Inter- rupt sources include the following: MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 32: Vector Generator

    M68000 operation is maintained. Here’s a typical scenario: when an interrupt is received, it is prioritized. Assuming there are no higher interrupts pending, it is posted to the M68000 core. The core responds with an MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 33: Interrupt Vector Register (Ivr)

    The MC68328 processor provides one interrupt vector for each interrupt level. The most significant 5 bits of the interrupt vector are user-programmable while the lower 3 bits reflect the interrupt level being serviced.
  • Page 34 In this case, users must clear the source of the interrupt. On re- set, this bit is clear to 0 (level-sensitive interrupt). 0 = Level-sensitive interrupt 1 = Edge-sensitive interrupt POL1 Polarity Control for Interrupt 1 0 = Negative polarity 1 = Positive polarity MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 35 (Mask Watchdog Timer Interrupt, Bit 3) This bit, while set, indicates that the watchdog timer interrupt is masked. It is set to 1 after reset. 0 = Enable WDT interrupt 1 = Mask WDT interrupt 2-10 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 36 (Mask External INT3, Bit 11) This bit, while set, indicates that the external interrupt INT3 is masked. It is set to 1 after reset. 0 = Enable INT3 interrupt 1 = Mask INT3 interrupt MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 2-11...
  • Page 37 (Mask IRQ3 Interrupt, Bit 18) This bit, while set, indicates that the external IRQ level-3 interrupt is masked. It is set to 1 after reset. 0 = Enable IRQ3 interrupt 1 = Mask IRQ3 interrupt 2-12 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 38: Interrupt Wakeup-Enable Register (Iwr)

    If there are multiple interrupt sources at that level, the software can prioritize them at that time. There is one interrupt vector for each interrupt level. The lower three bits of the interrupt vector constitute the interrupt level being acknowledged MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 2-13...
  • Page 39: Interrupt Status Register (Isr)

    1 = SPI master interrupting This bit indicates the PWM period rollover. Refer to the PWM section for details. This is a Level 4 interrupt. 0 = No PWM period rollover 1 = PWM period rolled over 2-14 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 40 1 to this status bit. Writing a 0 to this bit and the remainder of the bits in this register has no effect. 0 = No Level 7 interrupt pending 1 = Level 7 interrupt pending MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 2-15...
  • Page 41: Interrupt-Pending Register (Ipr)

    Figure 2-9. Group-Base Address Registers GROUP BASE ADDRESS (GBA31-GBA20) The group-base address field (the upper 12 bits of each base address register) selects the starting address for the group address range. The corresponding bits GBA31–GBA20 2-16 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 42: Group-Base Address Mask Registers

    ADDRESS MASK 23-16 UNUSED WAIT AM23 AM22 AM21 AM20 AM19 AM18 AM17 AM16 Address: $(FF)FFF110, 114, 118, 11C, 120, 124, 128, 12C Reset Value: $00010006 Figure 2-11. Chip-Select Registers for Group A and B MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 2-17...
  • Page 43 1 = 16-bit Read Only This bit sets the chip-select to read only. Otherwise, read and write accesses are allowed. Writes to read-only areas generate a bus error. 0 = Read/Write 1 = Read Only 2-18 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 44: Pcmcia 1.0 Support

    110 = Six wait states 111 = External DTACK 2.6 PCMCIA 1.0 SUPPORT The MC68328 processor supports PCMCIA 1.0 memory card chip-selects and read / write signals. To meet the fanout requirement, use external buffers to interface to the memory card.
  • Page 45 System Integration Module 2-20 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 46: Phase-Locked Loop And Power Control

    3.1 OVERVIEW The PLL is a flexible clock source for the MC68328. It provides a crystal-controlled master clock at frequencies from 10MHz to the maximum operational frequency in 32-kHz steps.
  • Page 47: Pll Control Register

    DISPLL Disable PLL This bit, while high, disables the PLL. The system clock is shut down and the MC68328 processor assumes its lowest power state. Only the 32 kHz clock runs. Refer to Section 3.4.3 for a description of the preferred method for system clock shutdown. Once the PLL is disabled, only a wake-up interrupt or reset can re-enable it.
  • Page 48: Pll Operation

    VCO frequency by 14 before it is fed to the rest of the divider chain. Dual-mod- ulus counters operate differently from other counters in that the overall divide ratio is depen- dent on two separate values, P and Q. Besides the power-saving advantage above a divisor MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 49: Normal Startup

    3.3.3 Normal Startup When the MC68328 processor is awakened from sleep mode by a system interrupt, the PLL achieves lock within a few milliseconds. The crystal oscillator is always on after initial pow- erup, so the crystal startup time is not a factor. The master clock starts operation after the PLL achieves lock.
  • Page 50: Power Control Module Overview

    The power control module improves power efficiency as it allocates power (clocks) to the CPU core and other modules in the MC68328 processor under software control. Clocks can be enabled in bursts. While executing tasks that require significant CPU resources, the clock can be enabled for extended periods of time.
  • Page 51 31 CLK32 periods, or approximately 1 msec. Note that the LCD DMA controller has access to the bus at all times and the SYSCLK—master clock to all peripherals— is continuously active. 1 msec SYSCLK CPUCLK Figure 3-5. Power Control Operation MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 52: Mpu Interface

    1 and the power controller is enabled, the clock is bursted to the CPU at a duty cycle of 1/31. While the WIDTH bits are 1F(hex), the clock is always on. While the WIDTH is zero, MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 53: Operation

    3.4.3 Operation This section describes how to use the power controller. 3.4.3.1 NORMAL OPERATION. When the MC68328 processor begins operation after reset, the power controller is disabled and the MC68EC000 clock runs continuously. To reduce the power consumed by the MC68EC000, the power controller is enabled when the PC EN bit is set.
  • Page 54: Lcd Controller Module

    16- or 8-word memory burst to fill the line buffer. The number of DMA clock cycles per transfer is programmable (1, 2, 3, or 4 clocks/transfer), which makes it more versatile to support systems with memory of different speeds. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 55: Line Buffer

    Because blinking or flickering will occur if all LCD pixel cells are synchronized, it is essential to program two 4-bit numbers, namely Xoff and Yoff in the FRC offset register (FOSR), to minimize flickering. As a general rule, select odd numbers that differ by 2. The optimal offset MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 56: Lcd Interface

    LCD panels and stays asserted for a duration of 8 pixel clock periods. Users can program the LP signal using software to be either active-high or active-low. See the POLCF register description for details. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 57: Panel I/F Timing

    Some LCD panels may use an active-low LFLM signal, LLP signal, LSCLK signal, and reversed pixel data. To change the polarities of these signals, set the first-line marker polar- ity (FLMPOL), line-pulse polarity (LPPOL), shift-clock polarity (SCLKPOL), and pixel polarity MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 58 In additional to the interface timing pins discussed above, an alternate crystal direction (LACD) pin in LCDC will toggle after a pre-programmed number of LFLM pulses. This pin prevents crystal degradation in the LCD panel. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 59 (c) 1-Bit LCD Data Bus (PBSIZ=00) LINE 1 LINE 2 LINE 3 LINE 4 LINE n LINE 1 SCLK [0,0] [0,1] [0,2] [0,78] [0,79] [0,m-2] [0,m-1] Figure 4-3. LCD Interface Timing for 4-, 2-, and 1-Bit Data Widths MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 60: Operation Overview

    MC68328 processor does not support. The actual limit is the number of rows that require high driving voltage. The MC68328 processor 4-bit LCD interface will drive up to 240 rows with a maximum of 1024 columns.
  • Page 61: Cursor Control Logic

    1 might be more pleasing than a linear-spaced scale such as 0, 5/16, 11/16, and 1 for certain graphics. A flexible mapping scheme lets users optimize the visual effect for the specific panel or application. MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 62 1 Bit Per Pixel Mode (0,0) (1,0) (2,0) (3,0) (4,0) (5,0) (6,0) (7,0) Display Mapping (X-8,Y-1) (X-7,Y-1) (X-6,Y-1) (X-5,Y-1) (X-4,Y-1) (X-3,Y-1) (X-2,Y-1) (X-1,Y-1) System ROM/RAM (Byte-oriented for clarity) Figure 4-5. Mapping of Memory Data on the Screen MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 63: Frc Offset Control

    4.5.8 Low-Power Mode Some panels may have a signal called PANEL_OFF that turns off the panel for low-power mode. In the MC68328 processor system, this signal is not supported. Instead, use a paral- lel I/O pin to perform this function.
  • Page 64: Dma Controller Overview

    For example, the average time latency for LCDCLK = 5MHz with 16-word burst is approximately 2.4 s. SYSCLK ADDRESS DATA Figure 4-6. Three Clock per LCD DMA Transfer (2 Wait States) MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 4-11...
  • Page 65 LCD Controller SYSCLK ADDRESS DATA Figure 4-7. One Clock per DMA Transfer (0 Wait State) 4-12 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 66: Register Descriptions

    VPW = virtual page width in pixels divided by c where c is 16 for black-and-white display and 8 for gray level. 4.7.2 Screen Format Registers 4.7.2.1 SCREEN WIDTH REGISTER (XMAX). UNUSED Address: $(FF)FFFA08 Reset Value: $03FF Figure 4-10. Screen Width Register XMAX MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 4-13...
  • Page 67: Screen Height Register (Ymax)

    CYP8 CYP7 CYP6 CYP5 CYP4 CYP3 CYP2 CYP1 CYP0 Address: $(FF)FFFA1A Reset Value: $0000 Figure 4-13. Cursor Y Position Register CYP8-CYP0 Cursor’s vertical starting position Y in pixel count (from 0 to YMAX). 4-14 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 68: Cursor Width & Height Register (Cwch)

    PBSIZ1 PBSIZ0 Address: $(FF)FFFA20 Reset Value: $00 Figure 4-16. Panel Interface Configuration Register PBSIZ1-PBSIZ0 Panel Bus Width LCD panel bus size. 00 = 1-bit 01 = 2-bit 10 = 4-bit 11 = unused MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 4-15...
  • Page 69: Polarity Configuration Register (Polcf)

    1 = Active positive edge of LCLK FLMPOL First-line marker polarity 0 = Active High 1 = Active Low LPPOL Line-pulse polarity 0 = Active-high 1 = Active-low PIXPOL Pixel polarity 0 = Active-high 1 = Active-low 4-16 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 70: Lacd (M) Rate Control Register (Acdrc)

    The internal LCDC logic will be switched off in step with the FLM pulse. DMA16 This bit controls the length of the DMA burst. 0 = 8 words burst length 1 = 16 words burst length MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 4-17...
  • Page 71: Last Buffer Address Register (Lbar)

    Controls the time interval between two lines; therefore, the frame refresh rate can also be finely adjusted. The register value must be greater than LBAR by 4 for black-and-white display and 8 for gray display. 4-18 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 72: Panning Offset Register (Posr)

    Gray palette code (bit position n=0, 1, 2) output for pixel-input data m (0 for pixel data 00, 1=01, 2=10, 3=11). This 3-bit code will then select one of 7 bitstreams of different densi- ties. See Section 4.5.5 Gray Palette Mapping for details. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 4-19...
  • Page 73: Bandwidth Calculation And Saving

    320pixels 2bitperpixel 2clock -------------------------------------------------------------------------------------- 16.67MHz 16bitbus (EQ 2) 4.8 s Thus, the percentage of host bus time taken up by the LCDC DMA is P 4.8` s ------------------ - (EQ 3) 69.4` s 6.92 4-20 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 74: Real-Time Clock Module

    The minute stopwatch performs a countdown with a resolution of one minute. It can gener- ate an interrupt after some length of time. Example: The LCD is to turn off after 5 minutes of inactivity. The minute stopwatch is programmed for 5 minutes and enabled. At consecutive MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 75: Registers

    The hours, minutes and seconds can be read or written at any time. After a write, the current time assumes the new values. Unused bits read 0. HOURS These 5 bits, when read, indicate the current hour and can be set to any value between 0 and 23. MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 76: Alarm Register (Rtcalrm)

    RTC Enable This bit enables the RTC. 1 = Enable RTC 0 = Disable RTC 38.4 38.4 kHz Reference Select 1 = Reference frequency is 38.4 kHz 0 = Reference frequency is 32.768 kHz MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 77: Interrupt Status Register (Rtcisr)

    1 = Alarm interrupt occurred 0 = No alarm interrupt occurred MIN FLAG If enabled, a minute flag is set on every minute tick. 1 = Minute tick occurred 0 = No minute tick occurred MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 78: Interrupt-Enable Register (Rtcienr)

    This bit enables the stopwatch interrupt. The stopwatch counts down and remains at dec- imal -1 until it is reprogrammed. Note: If this bit is enabled with -1 (decimal) in the stop- watch register, an interrupt will be posted on the next minute tick. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 79: Stopwatch Register (Stpwtch)

    This field contains the stopwatch countdown value. The highest allowable value is 62 min- utes. The countdown will not be activated again until a nonzero value (less than 63 min- utes) is written to the stopwatch-count register. MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 80: Timer

    SECTION 6 TIMER The MC68328 processor contains two identical general-purpose 16-bit timers with a pro- grammable prescaler and a software watchdog timer. Figure 6-1 shows the block diagram of the time module. TIMER CLOCK DID 16 SYSTEM CLOCK CONTROL REGISTER...
  • Page 81: General Purpose Timers

    TCR. When a capture or reference event occurs, the corresponding TSR bit is set and a maskable interrupt is issued. The timer is not activated after reset and must be programmed as users require. MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 82: Software Watchdog Timer

    This pin is the output of the timer and can be programmed to toggle or pulse whenever a “compare” event occurs. 6.4 PROGRAMMER’S MODEL Users may modify the general-purpose timer registers at any time. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 83: General Purpose Timer

    1 = Toggle output IRQEN Reference Event Interrupt-Enable This bit controls the generation of an interrupt on a reference-compare event. 0 = Disable interrupt on reference event 1 = Enable interrupt on reference event MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 84: Timer Prescaler Register

    6.4.1.4 TIMER-COMPARE REGISTER. Each “compare” register is a 16-bit register that contains the value that is compared with the free-running counter as part of the output- compare function. This is a memory-mapped read-write register. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 85: Timer-Compare Register

    0 = No capture event occurred 1 = Capture event occurred COMP Compare Event While high, this bit indicates that a “compare” event occurred. 0 = No compare event occurred 1 = Compare event occurred MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 86: Software Watchdog Timer

    6.4.2.3 WATCHDOG-CONTROL/STATUS REGISTER (WCR). UNUSED W/DRST LOCK WDEN Address: $(FF)FFF618 Reset Value: $0000 Figure 6-11. Watchdog-Control/Status Register MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 87 This bit indicates software reset status. 0 = Not reset 1 = Set when software reset is activated. This bit can be cleared only by writing a 0 to the bit in the control register. MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 88: Parallel Ports

    7.1.1 Port Operation There are three types of ports on the MC68328 processor. This section describes the func- tionality of each port. 7.1.1.1 BASIC PORT. Ports A, B, C, E, F, G, J and K are basic ports. Figure 7-1 illustrates their operation.
  • Page 89 Figure 7-3 illustrates the operation of the interrupt port. Port D does not have module signals associated with its signals; it is intended as a general-purpose, interrupt-generating port or a keyboard-input port. MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 90: Pullup Port

    7.1.2 Port A Port A is multiplexed with address lines A16-A23. Unused address pins can serve as parallel I/Os on a bit-by-bit basis. After reset, these signals default to their address function. Three MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 91: Port B

    BUSW pin. On reset, the data lines are connected to the pins. The programmer’s model for Port B is: DIRECTION DATA DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 Address: $FFFFF408 Reset Value: $0000 Figure 7-6. Port B Data/Direction Register MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 92: Port C

    I/O. The programmer’s model for port C follows. DIRECTION DATA DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 Address: $FFFFF410 Reset Value: $0000 Figure 7-8. Port C Data/Direction Register MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 93: Port D

    DIRECTION DATA DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 Address: $FFFFF418 Reset Value: $0000 Figure 7-10. Port D Data/Direction Register PULLUP UNUSED Address: $FFFFF41A Reset Value: $0000 Figure 7-11. Port D Pullup Register MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 94 These bits allow the interrupts to be presented to the interrupt controller block. EDGE ENABLE- IQEG[7:0] These bits, while high, enable edge interrupts. While low, level-sensitive interrupts are se- lected. The polarity of the edge (rising or falling) is selected by the POLARITY bits. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 95: Port E

    Bits that are configured as inputs will accept the data but the written data will not be accessible until their respective pins are configured as out- MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 96: Port F

    SELECT bits are low. The data bits may be written at any time. Bits that are con- figured as inputs will accept the written data but it will not be accessible until the respective MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 97: Port G

    DIR0 Address: $FFFFF430 Reset Value: $0000 Figure 7-18. Port G Data/Direction Register PULLUP SELECT SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 Address: $FFFFF432 Reset Value: $0000 Figure 7-19. Port G Select Register 7-10 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 98: Port J

    Table 7-4. Port J Bit Functions Port Function Other Function Bit 0 CSC0 Bit 1 CSC1 Bit 2 CSC2 Bit 3 CSC3 Bit 4 CSD0 Bit 5 CSD1 Bit 6 CSD2 Bit 7 CSD3 MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 7-11...
  • Page 99: Port K

    I/O function is connected to the pin; while low, the chip-select functions are connected. 7.1.10 Port K Port K is multiplexed with signals related to the serial peripheral interfaces and PCMCIA. The signals are identified below. 7-12 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 100 SELECT bits are low. The data bits may be written at any time. Bits that are configured as inputs will accept the written data but it will not be accessible until the respective pins MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 7-13...
  • Page 101: Port M

    DIR0 Address: $FFFFF448 Reset Value: $0000 Figure 7-24. Port M Data/Direction Register PULLUP SELECT SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 Address: $FFFFF44A Reset Value: $0000 Figure 7-25. Port M Select Register 7-14 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 102 The I/O functions are enabled after reset. PULLUP- PU[7:0] These bits enable the pullup resistors on the port. While high, the pullup resistors are en- abled; while low, the pullup resistors are disabled. The pullups are enabled on reset. 7-15 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 103 Parallel Ports 7-16 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 104: Serial Interface Signals

    There are 5 signals accessible to users and are described below. If users need any or all UART signals, the appropriate port bits can be programmed to assume their UART function. Refer to Section 7 Parallel Ports for information about programming the ports. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 105 GPIO General-Purpose Input/Output This bidirectional pin serves several functions. It can be a general-purpose input that: (1) can post interrupts on any transition, (2) is controlled by the GPIO bit in the baud register, MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 106: Sub-Block Description

    While the infrared interface is enabled, the transmitter produces a pulse that is 3/16 of a bit time for each 0 bit sent. The TXD port can directly drive an infrared LED or directly interface with popular IrDA transceivers. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 107: Receiver

    FIFO. While the IrDA interface is enabled, the receiver expects narrow pulses for each 0 bit received; otherwise, normal NRZ is expected. An IrDA transceiver, external to the MC68328 processor, transforms the infrared signal to an electrical signal.
  • Page 108: Uart Control Register

    While high, the receiver is in 1x mode where it samples the data stream on each rising edge of the bit clock. This bit resets to 0. 0 = 16x clock mode 1 = 1x clock mode MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 109 1 = CTS interrupt enabled RX FULL ENABLE While high, this bit enables an interrupt when the receiver FIFO is full. This bit resets to 0. 0 = RX FULL interrupt disabled 1 = RX FULL interrupt enabled MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 110: Baud Control Register

    This register controls the operation of the baud-rate generator and the GPIO pin and resets to $003F. GPIO GPIO GPIO BAUD GPIO DIVIDE UNUSED PRESCALER DELTA ADDRESS: $(FF)FFF902 Reset Value: $003F Figure 8-3. Baud Control Register MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 111 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 112: Receiver Register

    It indicates that the user’s software is not keeping up with the incoming data rate. This bit is updated and valid for each received character. 0 = No FIFO overrun 1 = FIFO overrun detected MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 113: Transmitter Register

    1 = Transmitter FIFO empty FIFO HALF This read-only bit indicates that the transmit FIFO is less than half full. 0 = Transmitter FIFO more than half full 1 = Transmitter FIFO less than half full 8-10 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 114 This feature is useful for software debugging. The CTS interrupt is cleared by writing 0 to this bit. 0 = CTS pin did not change state since last cleared 1 = CTS pin changed state MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 8-11...
  • Page 115: Miscellaneous Register

    This bit selects the function of the RTS pin. 0 = RTS pin is controlled by the RTS bit 1 = RTS pin is controlled by the receiver FIFO. When the FIFO is full (one slot remain- ing) RTS is negated. 8-12 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 116 This bit controls a loopback from transmitter to receiver in the IrDA interface. This bit is provided for system testing. 0 = No IR loop 1 = Connect IR transmit to IR receiver UNUSED These bits are unused and read 0. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 8-13...
  • Page 117 UART 8-14 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 118: Serial Peripheral Interface- Slave (Spis)

    9.1 OVERVIEW The SPI transfers data to the MC68328 processor from a peripheral device over a serial link. A clock, controlled by the external device, controls transfer. After counting 8 clock cycles, the shift register data moves to a read buffer, generating an interrupt in the process. Figure 9-1 is a block diagram of the slave SPI.
  • Page 119: Signal Descriptions

    SPIS state machine responds to clock edges for data transfer. 9.4 SPIS REGISTER This register controls the SPIS operation and reports its status. The data register contains the data transmitted by the external master. After reset, all bits are set to $0000. MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 120: Spi Slave Register

    This bit sets the phase relationship between SPSCLK and SPSRxD. Refer to Figure 9-2. 0 = Phase 0 (normal); data is captured on the leading edge of SPSCLK 1 = Phase 1; data is captured on the trailing edge of SPSCLK MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL...
  • Page 121 If the data buffer is not accessed before the next byte is received, it will be overwritten and the OVRWR bit will be set, post- ing an interrupt. MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 122: Serial Peripheral Interface- Master (Spim)

    SPIs that are popular on Motorola’s 6805 microcomputer chips. 10.1 OVERVIEW The SPIM transfers data between the MC68328 processor and peripheral devices in bursts over a serial link. Enable and clock signals control the exchange data between the two devices.
  • Page 123: Phase/Polarity Configurations

    Polarity = 1 inverts the data-clock relationships. This flexibility allows operation with most serial peripheral devices on the market. 10.3 SIGNAL DESCRIPTIONS The following signals are multiplexed with other signals in port K. Refer to Section 7.1.10 for more information. 10-2 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 124: Spim Registers

    This bit enables the SPIM. The enable should be asserted before initiating an exchange and should be negated after the exchange is complete. 0 = SPI master disable 1 = SPI master enable MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 10-3...
  • Page 125 0 = Active-high polarity (0=idle) 1 = Inverted polarity (1= idle) CLOCK COUNT These bits select the transfer length (up to 16 bits can be transferred). 0000 = 1 bit transfer 1111 = 16 bit transfer 10-4 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 126: Spim Data Register

    9, followed by the remaining 9 bits. NOTE Users should reload the data every time for each transfer before setting the XCH bit or the enable bit. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 10-5...
  • Page 127 SPI-Master 10-6 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 128: Pulse-Width Modulator

    At the beginning of each period, the con- tents of the buffer registers are loaded into the comparator for the next cycle. Sampled audio can be recreated by feeding a new sample value into the width register on each interrupt. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 11-1...
  • Page 129: Programmer's Model

    0 = No PWM period rollover 1 = PWM period rolled over IRQEN This bit controls the PWM interrupt. While this bit is low, the interrupt is disabled. 0 = PWM interrupt disabled 1 = PWM interrupt enabled 11-2 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 130 • The clock prescaler is released and begins counting. • The counter begins counting. • The comparators are enabled. • The IRQ bit is set indicating the start of a new period if IRQEN is set. MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 11-3...
  • Page 131: Period Register

    This read-only register is the current count value and can be read at any time without dis- turbing the counter. COUNT ADDRESS: $(FF)FFF506 Reset Value: 0000 Figure 11-7. Counter Register COUNT This is the current count value. 11-4 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 132 MC68328PV JTAGRST TOP VIEW BBUSW LCLK LACD PK0/SPMTXD0 PK1/SPMRXD0 PK2/SPMCLK0 PK3/SPSEN PK4/SPSRXD1 PK5/SPSCLK1 PK6/CE2 PK7/CE1 PM0/CTS PM1/RTS PM2/IRQ6 PM3/IRQ3 PM4/IRQ2 PM5/IRQ1 PM6/PENIRQ A16/PA0 Figure 12-1. MC68328 144-Lead Plastic Thin-Quad Flat Pack Pin Assignment MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 12-1...
  • Page 133: Pin Assignment

    11.00 BSC 0.433 BSC 22.00 BSC 0.866 BSC 11.00 BSC 0.433 BSC 0.25 REF 0.010 REF 0.039 REF 1.00 REF 0.16 0.004 0.09 0.006 Figure 13-2. MC68328 144-Lead Plastic Thin-Quad Flat Pack Specs 12-2 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 134: Maximum Ratings

    SECTION 13 ELECTRICAL CHARACTERISTICS—PRELIMINARY This section provides PRELIMINARY information on the maximum ratings for the MC68328 processor. 13.1 MAXIMUM RATINGS Rating Symbol Value Unit V CC Supply Voltage –0.3 to 7.0 V in Input Voltage –0.3 to 7.0 T L to T H...
  • Page 135 Table 13-2. AC Electrical Specifications—Chip-Select Read Cycle Timing PRELIMINARY 3.3 V Characteristic Unit Addr Valid to CS x Asserted — ASx to CSx CSx Width Asserted — CLKOUT to Addr CLKOUT to R/ W CLKOUT to OE 13-2 MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA...
  • Page 136 Electrical Characteristics: PRELIMINARY CLKOUT A0 - A31 D0 - D15 Figure 13-2. Chip-Select Read Cycle Timing (when the CPU is the Bus Master)—PRELIMINARY MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 13-3...
  • Page 137 Electrical Characteristics: PRELIMINARY MOTOROLA MC68328 DRAGONBALL PROCESSOR USER’S MANUAL 13-4...