Motorola PowerQUICC II MPC8280 Series Reference Manual page 482

SDRAM Machine
11.4.6.5 Last Data In to Precharge—Write Recovery
As demonstrated in Figure 11-24, this parameter, controlled by P/LSDMR[WRC], defines
the earliest timing for
Activate
CLK
ALE
CS
SDRAS
SDCAS
WE
MA[0–11] Row
DQM
Data
11.4.6.6 Refresh Recovery Interval (RFRC)
As represented in Figure 11-25, this parameter, controlled by P/LSDMR[RFRC], defines
the earliest timing for an
CLK
ALE
CS
SDRAS
SDCAS
A8 = 1
MA[0–11]
WE
DQM
PRETOACT = 3
Precharge
if needed
11-44
Freescale Semiconductor, Inc.
command after the last data was written to the SDRAM.
PRECHARGE
WRITE
Column
D0
D1 D2
Figure 11-24. WRC = 2 (2 Clock Cycles)
command after a
ACTIVATE
Auto refresh
Figure 11-25. RFRC = 4 (6 Clock Cycles)
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Last data in Deactivate
WRC = 2
D3
command.
REFRESH
RFRC = 4 (6 clocks)
RAx
Activate command
Bank A
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