Motorola PowerQUICC II MPC8280 Series Reference Manual page 1315

Size [Octets] Description
7 Preamble
1 SFD
6 Destination address
6 Source address
2 Length/type
2 MAC opcode
2 MAC parameter
42 Reserved
4 FCS
When flow-control mode is enabled (FPSMRx[FCE]) and the receiver identifies a
pause-flow control frame sent to individual or broadcast addresses, transmission stops for
the time specified in the control frame. During this pause, only the out-of-sequence frame
is sent. Normal transmission resumes after the pause timer stops counting. If another
pause-control frame is received during the pause, the period changes to the new value
received.
36.7 CAM Interface
The MPC8280 internal address recognition logic can be used in combination with an
external CAM. When using a CAM, the FCC must be in promiscuous mode
(FPSMRx[PRO] = 1). See Section 36.12, "Ethernet Address Recognition."
The Ethernet controller writes two 32-bit accesses to the CAM and then reads the result in
a 32-bit access. If the high bit of the result is set, the frame is rejected; otherwise, the lower
16 bits are attached to the end of the frame.
When an external CAM is used for address filtering, users can choose to either discard
rejected frames (FPSMR[ECM] = 0) or receive rejected frames and signal the CAM miss
in the RxBD (FPSMR[ECM] = 1).
MOTOROLA
Freescale Semiconductor, Inc.
Table 36-1. Flow Control Frame Structure
Value
01-80C2-00-00-01
88-08
00-01
up to
0xFFFE
—
Chapter 36. Fast Ethernet Controller
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Comment
Start frame delimiter
Multicast address reserved for use in MAC frames
Control frame type
Pause command
Pause period measured in slot times, most-significant
octet first with a two time-slot resolution.
Note: Because the pause period has a resolution of two
time slots, the value programmed in this field is rounded
up to the nearest even number before being used, as
follows:
MAC Parameter ValuePause Period
0 none
1 or 2 2 x slot time
3 or 4 4 x slot time
......
Frame check sequence (CRC)
CAM Interface
36-9