Motorola PowerQUICC II MPC8280 Series Reference Manual page 706

Programming the Parallel I/O Registers
Exception
Reset On an external reset, the IDMA immediately aborts the channel operation, returns to the idle state, and
clears IDSR. If reset is detected when a bus transaction is in progress, the transaction is terminated, the
control and address/data pins are three-stated, and bus mastership is released.
Transfer When a fatal error occurs during a bus transaction, a bus error exception is used to abort the transaction
Error and systematically terminate channel operation. The IDMA terminates the current bus transaction, signals
an error in the SDSR, and signals an interrupt if the corresponding bit in the SDMR is set. The CPM must
be reset before IDMA operation is restarted. Any data previously read from the source into the internal
storage is lost, however, issuing a
Note: Any source or destination device for an operand under IDMA handshake control for single-address
transfers may need to monitor TEA to detect a bus exception for the current bus transaction. TEA
terminates the transaction immediately and negates DACK, which is used to control the transfer to/from
the device.
19.10.1 Externally Recognizing IDMA Operand Transfers
The following ways can be used determine externally that the IDMA is executing a bus
transaction:
• The TC[2] signal (programmed in DCM[TC2]) or SDMA channels can be
programmed to a unique code that identifies an IDMA transfer.
• The DACK signal shows accesses to the peripheral device. DACK activates on either
the source or destination bus transactions, depending on DCM[S/D].
19.11 Programming the Parallel I/O Registers
The parallel I/O registers control the use of the external pins of the chip. Each pin can be
used for different purposes. See Table 19-12, Table 19-13 and Table 19-14 (optional) for
the proper parallel I/O register programming dedicating the proper external ports to the four
IDMA channels' external I/O signals.
Each port is controlled by five I/O registers: PPAR, PSOR, PDIR, PODR, and PDAT. Each
bit in these registers controls the external pin of the same location.
• PPARC selects the pins general purpose(0)/dedicated(1) mode for port C.
• PDIRC select the pins input or inout (0)/output(1) mode for port C.
• PODRC selects the open drain pins for port C.
• PSORC selects the pins dedicated1(0)/dedicated2(1) mode for port C.
• PPARA, PDIRA, PODRA, and PSORA control port A in the same way.
• PPARD, PDIRD, PODRD, and PSORD control port D in the same way.
• The default is the value that is seen by the IDMA channel on the pin (input or inout
mode only—PDIR[PN] = 0) if a PSORx register bit is set to the complement value
19-30
Freescale Semiconductor, Inc.
Table 19-11. IDMA Bus Exceptions
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