Motorola PowerQUICC II MPC8280 Series Reference Manual page 1359

Chapter 39
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) allows the MPC8280 to exchange data between other
MPC8280 chips, the MPC860, the MC68360, the MC68302, the M68HC11 and M68HC05
microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D
converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire
interface (receive, transmit, clock and slave select). The SPI block consists of transmitter
and receiver sections, an independent baud-rate generator, and a control unit. The
transmitter and receiver sections use the same clock, which is derived from the SPI baud
rate generator in master mode and generated externally in slave mode. During an SPI
transfer, data is sent and received simultaneously.
Because the SPI receiver and transmitter are double-buffered, as shown in Figure 39-1, the
effective FIFO size (latency) is 2 characters. The SPI's msb is shifted out first. When the
SPI is disabled in the SPI mode register (SPMODE[EN] = 0), it consumes little power.
60x Bus
SPI Mode Register
Counter
SPISEL
MOTOROLA
Freescale Semiconductor, Inc.
Transmit_Register
RxD IN_CLK
Pins Interface
SPIMOSI SPIMISO
Figure 39-1. SPI Block Diagram
Chapter 39. Serial Peripheral Interface (SPI)
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Peripheral Bus
Receive_Register
Shift_Register
TxD
SPIBRG
SPICLK
BRGCLK
39-1