Motorola PowerQUICC II MPC8280 Series Reference Manual page 685

Figure 19-6 shows an example of the three IDMA transfer stages.
First Phase
128
EOB (source)
96
64
32
0
after first read after first write
Steady-State Phase (2 transfers in this case)
after second read
after second write
Last Phase
after last read
after last write
Figure 19-6. Example IDMA Transfer Buffer States for a Memory-to-Memory
19.5.1.1 External Request Mode
Memory-to-memory transfers can be configured to operate in external request mode
(DCM[ERM] = 1). In external request mode, every read transfer is triggered by the
assertion of DREQ. When the transfer buffer is full, the first write transfer is done
automatically. Additional write transfers, if needed, are triggered by DREQ assertions.
Because at least one of the transfer sizes (STS or DTS) equals SS_MAX, every DREQ
assertion causes one transfer to the smaller (in STS/DTS terms) bus. If STS = DTS,
asserting DREQ triggers one read transfer automatically followed by one write transfer.
MOTOROLA
Freescale Semiconductor, Inc.
EOB (destination)
Read size = EOB(source) + SS_MAX
Write size = EOB(destination) + SS_MAX
Note: After phase 1, less than 32 bytes (a burst) will
remain in the internal buffer.
Read size = SS_MAX
Write size = SS_MAX
Read size = remainder data of BD
Write size = all data left
Transfer
(Size = 128 Bytes)
Chapter 19. SDMA Channels and IDMA Emulation
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after third read
after third write
IDMA Transfers
Read size = SS_MAX
Write size = SS_MAX
19-9