Motorola PowerQUICC II MPC8280 Series Reference Manual page 1344

HDLC Mode Register (FPSMR)
37.6 HDLC Mode Register (FPSMR)
When an FCC is configured for HDLC mode, the FPSMR is used as the HDLC mode
register, shown in Figure 37-3.
0
Field NOF
Reset
R/W
Addr
16 17
Field NBL
Reset
R/W
Addr
The FPSMR fields are described in Table 37-6.
Bits Name
0–3 NOF Number of flags. Minimum number of flags between or before frames (0–15 flags). If NOF = 0000,
no flags are inserted between the frames. Thus, for back-to-back frames, the closing flag of one
frame is immediately followed by the opening flag of the next frame.
4 FSE Flag sharing enable. This bit is valid only if GFMR[RTSM] is set.
0 Normal operation
1 If NOF = 0000, a single shared flag is transmitted between back-to-back frames. Other values of
NOF are decremented by 1 when FSE is set. This is useful in signaling system #7 applications.
5 MFF Multiple frames in FIFO. Setting MFF applies only when in RTS mode (GFMRx[RTSM] = 1).
0 Normal operation. The transmit FIFO buffer must never contain more than one HDLC frame. The
CTS lost status is reported accurately on a per-frame basis. The receiver is not affected by this bit.
1 The transmit FIFO buffer can contain multiple frames, but lost CTS is not guaranteed to be
reported on the exact buffer/frame it occurred on. This option, however, can improve the
performance of HDLC transmissions for small back-to-back frames or if the user prefers to
strongly limit the number of flags sent between frames. MFF does not affect the receiver.
Refer to note 1 at the end of this table.
7–8 — Reserved, should be cleared.
9 TS Time stamp
0 Normal operation.
1 A 32-bit time stamp is added at the beginning of the receive BD data buffer, thus the buffer pointer
must be (32-byte aligned - 4). The BD's data length does not include the time stamp. See
Section 14.3.8, "RISC Time-Stamp Control Register (RTSCR)."
10–15 — Reserved, should be cleared.
37-8
Freescale Semiconductor, Inc.
3 4 5 6
FSE MFF
0000_0000_0000_0000
0x11304 (FPSMR1), 0x11324 (FPSMR2), 0x11324 (FPSMR3)
—
0000_0000_0000_0000
0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11326 (FPSMR3)
Figure 37-3. HDLC Mode Register (FPSMR)
Table 37-6. FPSMR Field Descriptions
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8 9 10
— TS
R/W
23 24 25 26
CRC
R/W
1
Description
15
—
31
—
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