Motorola PowerQUICC II MPC8280 Series Reference Manual page 491

When using page-based interleaving, the internal bank-select signals that are mutilplexed
over the address lines are determined only by PSDMR[BSMA] during the
command. The output of the BNKSEL pins are not affected by the PSDMR[BSMA] value.
During a /
READ WRITE
Table 11-24. SDRAM Device Address Port during
"A[0–14]" A[15–16]
— Internal bank select
Because AP alternates with A[7] of the row lines, set PSDMR[SDA10] = 011. This outputs
A[7] on the SDA10 line during the
CBR commands.
Table 11-25 shows the register configuration. Not shown are PSRT and MPTPR, which
should be programmed according to the device refresh requirements:
Table 11-25. Register Settings (Page-Based Interleaving)
Register
BRx BA Base address
PS00 = 64-bit port size
DECC00
WP0
MS010 = SDRAM-60x bus
ORx AM1111_1100_0000
LSDAM00000
BPD01
ROWST0110
PSDMR PBI1
RFEN1
OP000
SDAM011
BSMA010
SDA10011
RFRC from device data sheet
PRETOACT from device data sheet
11.4.13 SDRAM Configuration Example (Bank-Based
Interleaving)
Consider the following SDRAM organization:
• Eight 64 Mbit devices, each organized as 8M x 8bits
• Each device has four internal banks, 12 rows, and 9 columns
MOTOROLA
Freescale Semiconductor, Inc.
command, the address port should look like Table 11-24.
A[17]
Don't care
ACTIVATE
Chapter 11. Memory Controller
For More Information On This Product,
Go to: www.freescale.com
/
READ WRITE
A[18] A[19]
AP Don't care
command and AP during
Settings
EMEMC0
ATOM00
DR0
V 1
NUMR011
PMSEL0
IBID0
ACTTOROW from device data sheet
BL0
LDOTOPRE from device data sheet
WRC from device data sheet
EAMUX0
BUFCMD0
CL from device data sheet
SDRAM Machine
ACTIVATE
Command
A[20–28] A[29–31]
Column n.c.
/ and
READ WRITE
11-53